HH(`Foundation-v8A$arm,foundation-aarch64arm,vexpress"1chosenaliases*=/smb@8000000/iofpga@3,00000000/uart@90000*E/smb@8000000/iofpga@3,00000000/uart@a0000*M/smb@8000000/iofpga@3,00000000/uart@b0000*U/smb@8000000/iofpga@3,00000000/uart@c0000cpus"1cpu@0]cpu arm,armv8im ~spin-tablecpu@1]cpu arm,armv8im ~spin-tablecpu@2]cpu arm,armv8im ~spin-tablecpu@3]cpu arm,armv8im ~spin-tablel2-cache0cachememory@80000000]memory itimerarm,armv8-timer0   pmuarm,armv8-pmuv30<=>?watchdog@2a440000arm,sbsa-gwdt i*D*E smb@8000000arm,vexpress,v2m-p1simple-busrs1"1x  ?              !!""##$$%%&&''(())**ethernet@2,02000000smsc,lan91c111 iclk24mhz fixed-clockn6 %v2m:clk24mhzrefclk1mhz fixed-clockB@%v2m:refclk1mhzrefclk32khz fixed-clock%v2m:refclk32khziofpga@3,00000000 simple-bus"1 sysreg@10000arm,vexpress-sysregiuart@90000arm,pl011arm,primecelli 8?uartclkapb_pclkuart@a0000arm,pl011arm,primecelli 8?uartclkapb_pclkuart@b0000arm,pl011arm,primecelli 8?uartclkapb_pclkuart@c0000arm,pl011arm,primecelli 8?uartclkapb_pclkvirtio-block@130000 virtio,mmioi*interrupt-controller@2c001000%arm,cortex-a15-gicarm,cortex-a9-gic"K@i,, ,@ ,`    modelcompatibleinterrupt-parent#address-cells#size-cellsserial0serial1serial2serial3device_typeregnext-level-cacheenable-methodcpu-release-addrphandleinterruptsclock-frequencytimeout-secarm,v2m-memory-mapranges#interrupt-cellsinterrupt-map-maskinterrupt-map#clock-cellsclock-output-namesclocksclock-namesinterrupt-controller