[8U(UL ARM Juno development board (r0)arm,junoarm,vexpress"1refclk7372800hz fixed-clock=Jp Zjuno:uartclkm9clk48mhz fixed-clock=Jl Zclk48mhzm=clk50mhz fixed-clock=JZsmc_clkm refclk100mhz fixed-clock=J Zapb_pclkm refclk400mhz fixed-clock=Jׄ Zfaxi_clkm3smb@8000000 simple-bus"1xu | DEF    clk24mhz fixed-clock=Jn6Zjuno_mb:clk24mhzmclk25mhz fixed-clock=J}x@Zjuno_mb:clk25mhzmrefclk1mhz fixed-clock=JB@Zjuno_mb:refclk1mhzmrefclk32khz fixed-clock=JZjuno_mb:refclk32khzmmotherboardarm,vexpress,v2p-p1simple-bus"1|u V2M-JunoRrs1mcc-sb-3v3regulator-fixed MCC_SB_3V32Z2Zmgpio-keys gpio-keyspower-button.2@NtYPOWER _home-button.2@NfYHOME _rlock-button.2@NYRLOCK _vol-up-button.2@NsYVOL+ _vol-down-button.2@NrYVOL- _nmi-button.2@NcYNMI _flash@0,00000000arm,vexpress-flashcfi-flasheafs vz disabledethernet@2,00000000smsc,lan9118smsc,lan9115 vmiiiofpga@3,00000000 simple-bus"1u sysctl@20000arm,sp810arm,primecellv refclktimclkapb_pclk=0Ztimerclken0timerclken1timerclken2timerclken3 mapbregs@10000sysconsimple-mfdvled0register-bit-led- Yvexpress:0 4heartbeatJonled1register-bit-led- Yvexpress:14mmc0Joffled2register-bit-led- Yvexpress:24cpu0Joffled3register-bit-led- Yvexpress:34cpu1Joffled4register-bit-led- Yvexpress:44cpu2Joffled5register-bit-led-  Yvexpress:54cpu3Joffled6register-bit-led-@ Yvexpress:6Joffled7register-bit-led- Yvexpress:7Joffmmci@50000arm,pl180arm,primecellvXf mclkapb_pclkkmi@60000arm,pl050arm,primecellv KMIREFCLKapb_pclkkmi@70000arm,pl050arm,primecellv KMIREFCLKapb_pclkwdt@f0000arm,sp805arm,primecellv wdogclkapb_pclktimer@110000arm,sp804arm,primecellv timclken1timclken2apb_pclktimer@120000arm,sp804arm,primecellv timclken1timclken2apb_pclkrtc@170000arm,pl031arm,primecellv  apb_pclkgpio@1d0000arm,pl061arm,primecellv  apb_pclkr|mtimer@2a810000arm,armv7-timer-memv*J"1u disabledframe@2a830000 <v*mhu@2b1f0000arm,mhuarm,primecellv+$#mhu_lpri_rxmhu_hpri_rx  apb_pclkm/iommu@2b500000arm,mmu-401arm,smmu-v1v+P(( disabledm.iommu@2b600000arm,mmu-401arm,smmu-v1v+`** minterrupt-controller@2c010000arm,gic-400arm,cortex-a15-gic@v,, , , "|1  ?u,mv2m@0arm,gic-v2m-framevm-v2m@10000arm,gic-v2m-framevv2m@20000arm,gic-v2m-framevv2m@30000arm,gic-v2m-framevtimerarm,armv8-timer0 ?? ? ?etf@20010000 arm,coresight-tmcarm,primecellv   apb_pclk ports"1port@0vendpoint! mport@1vendpoint! m,tpiu@20030000!arm,coresight-tpiuarm,primecellv   apb_pclk portendpoint!m*funnel@20040000#arm,coresight-funnelarm,primecellv   apb_pclk ports"1port@0vendpoint!m port@1vendpoint!mport@2vendpoint!mport@3vendpoint!metr@20070000 arm,coresight-tmcarm,primecellv 1  apb_pclk portendpoint!m+stm@20100000 arm,coresight-stmarm,primecell v (8stm-basestm-stimulus-base  apb_pclk portendpoint!mcpu-debug@22010000&arm,coresight-cpu-debugarm,primecellv"  apb_pclk Betm@22040000"arm,coresight-etm4xarm,primecellv"  apb_pclk Bportendpoint!mfunnel@220c0000#arm,coresight-funnelarm,primecellv"   apb_pclk ports"1port@0vendpoint!mport@1vendpoint!mport@2vendpoint!mcpu-debug@22110000&arm,coresight-cpu-debugarm,primecellv"  apb_pclk Betm@22140000"arm,coresight-etm4xarm,primecellv"  apb_pclk Bportendpoint!mcpu-debug@23010000&arm,coresight-cpu-debugarm,primecellv#  apb_pclk Betm@23040000"arm,coresight-etm4xarm,primecellv#  apb_pclk Bportendpoint!m funnel@230c0000#arm,coresight-funnelarm,primecellv#   apb_pclk ports"1port@0vendpoint!mport@1vendpoint! mport@2vendpoint!!m%port@3vendpoint!"m'port@4vendpoint!#m)cpu-debug@23110000&arm,coresight-cpu-debugarm,primecellv#  apb_pclk B$etm@23140000"arm,coresight-etm4xarm,primecellv#  apb_pclk B$portendpoint!%m!cpu-debug@23210000&arm,coresight-cpu-debugarm,primecellv#!  apb_pclk B&etm@23240000"arm,coresight-etm4xarm,primecellv#$  apb_pclk B&portendpoint!'m"cpu-debug@23310000&arm,coresight-cpu-debugarm,primecellv#1  apb_pclk B(etm@23340000"arm,coresight-etm4xarm,primecellv#4  apb_pclk B(portendpoint!)m#replicator@20120000/arm,coresight-dynamic-replicatorarm,primecellv   apb_pclk ports"1port@0vendpoint!*mport@1vendpoint!+mport@2vendpoint!,m sram@2e000000arm,juno-sram-nsmmio-sramv."1u.scp-shmem@0arm,juno-scp-shmemvscp-shmem@200arm,juno-scp-shmemvm0pcie@40000000<arm,juno-r1-pcieplda,xpressrich3-axipci-host-ecam-genericFpciv@R\"1Tu_PPB@@|m- disabledx.scpi arm,scpi/0clocksarm,scpi-clocksclocks-0arm,scpi-dvfs-clocks= Zatlclkaplclkgpuclkm?clocks-1arm,scpi-variable-clocks=Zpxlclkm5power-controllerarm,scpi-power-domainsm sensorsarm,scpi-sensorsm1thermal-zonespmicd1socd1big-clusterd1 disabledlittle-clusterd1 disabledgpu0d1 disabledgpu1d1 disablediommu@7fb00000arm,mmu-401arm,smmu-v1v__ disabledm2iommu@7fb10000arm,mmu-401arm,smmu-v1vccm4iommu@7fb20000arm,mmu-401arm,smmu-v1vaam7iommu@7fb30000arm,mmu-401arm,smmu-v1veem<dma@7ff00000arm,pl330arm,primecellv!/ lXYZ[\lmnoH12222222223 apb_pclkhdlcd@7ff50000 arm,hdlcdv ]145pxlclkportendpoint!6m;hdlcd@7ff60000 arm,hdlcdv U175pxlclkportendpoint!8m:uart@7ff80000arm,pl011arm,primecellv S9 uartclkapb_pclki2c@7ffa0000snps,designware-i2cv"1 hJ= hdmi-transmitter@70 nxp,tda998xvpportendpoint!:m8hdmi-transmitter@71 nxp,tda998xvqportendpoint!;m6ohci@7ffb0000 generic-ohciv t1<=ehci@7ffc0000 generic-ehciv u1<=memory-controller@7ffd0000arm,pl354arm,primecellvVW  apb_pclkmemory@80000000Fmemory vtlx@60000000 simple-bus"1u`| aliasesR/uart@7ff80000chosenZserial0:115200n8psci arm,psci-0.2fsmccpus"1cpu-mapcluster0core0Bcore1Bcluster1core0Bcore1B$core2B&core3B(idle-statesmpscicpu-sleep-0arm,idle-statez,m@cluster-sleep-0arm,idle-statez mAcpu@0arm,cortex-a57arm,armv8vFcpupsci@@-:>?K@A[mcpu@1arm,cortex-a57arm,armv8vFcpupsci@@-:>?K@A[mcpu@100arm,cortex-a53arm,armv8vFcpupsci@@-:B?K@A[Bmcpu@101arm,cortex-a53arm,armv8vFcpupsci@@-:B?K@A[Bm$cpu@102arm,cortex-a53arm,armv8vFcpupsci@@-:B?K@A[Bm&cpu@103arm,cortex-a53arm,armv8vFcpupsci@@-:B?K@A[Bm(l2-cache0cache @m>l2-cache1cache@mBpmu-a57arm,cortex-a57-pmunpmu-a53arm,cortex-a53-pmu0n$&( modelcompatibleinterrupt-parent#address-cells#size-cells#clock-cellsclock-frequencyclock-output-namesphandleranges#interrupt-cellsinterrupt-map-maskinterrupt-maparm,hbiarm,vexpress,sitearm,v2m-memory-mapregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-ondebounce-intervalwakeup-sourcelinux,codelabelgpioslinux,part-proberegbank-widthstatusinterruptsphy-modereg-io-widthsmsc,irq-active-highsmsc,irq-push-pullclocksvdd33a-supplyvddvario-supplyclock-namesassigned-clocksassigned-clock-parentsoffsetlinux,default-triggerdefault-statemax-frequencyvmmc-supplygpio-controller#gpio-cellsinterrupt-controllerframe-numberinterrupt-names#mbox-cells#iommu-cells#global-interruptsdma-coherentpower-domainsmsi-controllerslave-moderemote-endpointiommusreg-namescpudevice_typebus-rangelinux,pci-domainmsi-parentiommu-map-maskiommu-mapmboxesshmemclock-indicesnum-domains#power-domain-cells#thermal-sensor-cellspolling-delaypolling-delay-passivethermal-sensors#dma-cells#dma-channels#dma-requestsi2c-sda-hold-time-nsserial0stdout-pathmethodentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-idle-statescapacity-dmips-mhzinterrupt-affinity