Š žķ"8„(–L)Qualcomm Technologies, Inc. IPQ8074-HK01qcom,ipq8074-hk01qcom,ipq8074 ,soc =’’’’ simple-buspinctrl@1000000qcom,ipq8074-pinctrlD0 HŠSco„• serial4-pinmuxgpio23gpio24 ¢blsp4_uart1«ŗ•i2c-0-pinmuxgpio42gpio43 ¢blsp1_i2c«ŗ•spi-0-pinsgpio38gpio39gpio40gpio41 ¢blsp0_spi«ŗ•hsuart-pinsgpio46gpio47gpio48gpio49 ¢blsp2_uart«ŗ•qpic-pinsbgpio1gpio3gpio4gpio5gpio6gpio7gpio8gpio10gpio11gpio12gpio13gpio14gpio15gpio16gpio17¢qpic«ŗ• interrupt-controller@b000000qcom,msm-qgic2o„D  •timerarm,armv8-timer0Htimer@b120000 =arm,armv7-timer-memD Ē$ųframe@b120000×HD   frame@b123000× H D 0 ädisabledframe@b124000× H D @ ädisabledframe@b125000× H D P ädisabledframe@b126000× H D ` ädisabledframe@b127000× H D p ädisabledframe@b128000× HD € ädisabledgcc@1800000qcom,gcc-ipq8074D€ėų•serial@78b3000%qcom,msm-uartdm-v1.4qcom,msm-uartdmD‹0 H4&  coreiface"defaultäokdma@7884000qcom,bam-v1.7.0Dˆ@° Hī bam_clk0;•serial@78af000%qcom,msm-uartdm-v1.4qcom,msm-uartdmDŠš Hk"  coreiface ädisabledserial@78b1000%qcom,msm-uartdm-v1.4qcom,msm-uartdmD‹ H2$  coreifaceCHtxrx"defaultäokspi@78b5000qcom,spi-qup-v2.2.1 D‹P H_Rśš€  coreifaceC  Htxrx"defaultäokm25p80@0 jedec,spi-norDRśš€i2c@78b6000qcom,i2c-qup-v2.2.1 D‹` H`  ifacecoreĒ€CHrxtx"defaultäoki2c@78b7000qcom,i2c-qup-v2.2.1 D‹p Ha  ifacecoreĒ† CHrxtx ädisableddma@7984000qcom,bam-v1.7.0D˜@  H’) bam_clk0;äok•nand@79b0000qcom,ipq8074-nandD› *)  coreaonC Htxrxcmd "defaultäoknand@0Ddv‰phy@86000qcom,ipq8074-qmp-pcie-phyD`˜s  pipe_clk£pcie20_phy0_pipe_clk¶NO ½phycommonäok• pci@20000000qcom,pcie-ipq8074 D   Ø ÉdbielbiparfconfigÓpcißš’ś   pciephy0= ‚ 0 0Š H4msi„#€6KNOS(tqrop ifaceaxi_maxi_sahbaux8¶uvwxyz{/½pipesleepstickyaxi_maxi_sahbaxi_m_stickyäok D :phy@8e000qcom,ipq8074-qmp-pcie-phyDą˜y  pipe_clk£pcie20_phy1_pipe_clk¶RS ½phycommonäok• pci@10000000qcom,pcie-ipq8074 D Ø€ ÉdbielbiparfconfigÓpcißš’ś   pciephy0=  ‚00Š HUmsi„#€6Ž‘(zwxuv ifaceaxi_maxi_sahbaux8¶|}~€‚/½pipesleepstickyaxi_maxi_sahbaxi_m_stickyäok D =cpus cpu@0Ócpuarm,cortex-a53arm,armv8DO `pscicpu@1Ócpuarm,cortex-a53arm,armv8`psciDO cpu@2Ócpuarm,cortex-a53arm,armv8`psciDO cpu@3Ócpuarm,cortex-a53arm,armv8`psciDO l2-cachecachen• psci arm,psci-1.0gsmcpmuarm,armv8-pmuv3 Hclockssleep_clk fixed-clockĒ€ėxo fixed-clockĒ$ųėaliasesz/soc/serial@78b3000‚/soc/serial@78b1000chosenŠserial0memory@40000000ÓmemoryD@  modelcompatible#address-cells#size-cellsinterrupt-parentrangesreginterruptsgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellsphandlepinsfunctiondrive-strengthbias-disableclock-frequencyframe-numberstatus#clock-cells#reset-cellsclocksclock-namespinctrl-0pinctrl-names#dma-cellsqcom,eedmasdma-namesspi-max-frequencynand-ecc-strengthnand-ecc-step-sizenand-bus-width#phy-cellsclock-output-namesresetsreset-namesreg-namesdevice_typelinux,pci-domainbus-rangenum-lanesphysphy-namesinterrupt-namesinterrupt-map-maskinterrupt-mapperst-gpionext-level-cacheenable-methodcache-levelserial0serial1stdout-path