L@8H(LH ',Qualcomm Technologies, Inc. SDM845 MTP2qcom,sdm845-mtpaliases=/soc/geniqup@8c0000/i2c@880000B/soc/geniqup@8c0000/i2c@884000G/soc/geniqup@8c0000/i2c@888000L/soc/geniqup@8c0000/i2c@88c000Q/soc/geniqup@8c0000/i2c@890000V/soc/geniqup@8c0000/i2c@894000[/soc/geniqup@8c0000/i2c@898000`/soc/geniqup@8c0000/i2c@89c000e/soc/geniqup@ac0000/i2c@a80000j/soc/geniqup@ac0000/i2c@a84000o/soc/geniqup@ac0000/i2c@a88000u/soc/geniqup@ac0000/i2c@a8c000{/soc/geniqup@ac0000/i2c@a90000/soc/geniqup@ac0000/i2c@a94000/soc/geniqup@ac0000/i2c@a98000/soc/geniqup@ac0000/i2c@a9c000/soc/geniqup@8c0000/spi@880000/soc/geniqup@8c0000/spi@884000/soc/geniqup@8c0000/spi@888000/soc/geniqup@8c0000/spi@88c000/soc/geniqup@8c0000/spi@890000/soc/geniqup@8c0000/spi@894000/soc/geniqup@8c0000/spi@898000/soc/geniqup@8c0000/spi@89c000/soc/geniqup@ac0000/spi@a80000/soc/geniqup@ac0000/spi@a84000/soc/geniqup@ac0000/spi@a88000/soc/geniqup@ac0000/spi@a8c000/soc/geniqup@ac0000/spi@a90000/soc/geniqup@ac0000/spi@a94000/soc/geniqup@ac0000/spi@a98000/soc/geniqup@ac0000/spi@a9c000"/soc/geniqup@ac0000/serial@a84000chosenserial0:115200n8memory@80000000memory reserved-memory  memory@85fc0000 memory@85fe0000 2qcom,cmd-db memory@86000000  memory@86200000 cpus cpu@0cpu 2qcom,kryo385 #psci1l2-cache2cache1l3-cache2cachecpu@100cpu 2qcom,kryo385 #psci1l2-cache2cache1cpu@200cpu 2qcom,kryo385 #psci1l2-cache2cache1cpu@300cpu 2qcom,kryo385 #psci1l2-cache2cache1cpu@400cpu 2qcom,kryo385 #psci1l2-cache2cache1cpu@500cpu 2qcom,kryo385 #psci1l2-cache2cache1cpu@600cpu 2qcom,kryo385 #psci1 l2-cache2cache1 cpu@700cpu 2qcom,kryo385 #psci1 l2-cache2cache1 pmu2arm,armv8-pmuv3 Btimer2arm,armv8-timer0Bclocksxo-board 2fixed-clockMZI jxo_boardsleep-clk 2fixed-clockMZhwlock2qcom,tcsr-mutex }  smem 2qcom,smem  psci 2arm,psci-1.0*smcsoc   2simple-busclock-controller@1000002qcom,gcc-sdm845 Mgeniqup@8c00002qcom,geni-se-qup ` m-ahbs-ahbde   disabledi2c@8800002qcom,geni-i2c @seDdefault BY  disabledspi@8800002qcom,geni-spi @seDdefault BY  disabledi2c@8840002qcom,geni-i2c @@seFdefault BZ  disabledspi@8840002qcom,geni-spi @@seFdefault BZ  disabledi2c@8880002qcom,geni-i2c @seHdefault B[  disabledspi@8880002qcom,geni-spi @seHdefault B[  disabledi2c@88c0002qcom,geni-i2c @seJdefault B\  disabledspi@88c0002qcom,geni-spi @seJdefault B\  disabledi2c@8900002qcom,geni-i2c @seLdefault B]  disabledspi@8900002qcom,geni-spi @seLdefault B]  disabledi2c@8940002qcom,geni-i2c @@seNdefault B^  disabledspi@8940002qcom,geni-spi @@seNdefault B^  disabledi2c@8980002qcom,geni-i2c @sePdefault B_  disabledspi@8980002qcom,geni-spi @sePdefault B_  disabledi2c@89c0002qcom,geni-i2c @seRdefault B`  disabledspi@89c0002qcom,geni-spi @seRdefault B`  disabledgeniqup@ac00002qcom,geni-se-qup ` m-ahbs-ahbfg  okayi2c@a800002qcom,geni-i2c @seTdefault Ba  disabledspi@a800002qcom,geni-spi @seTdefault  Ba  disabledi2c@a840002qcom,geni-i2c @@seVdefault! Bb  disabledspi@a840002qcom,geni-spi @@seVdefault" Bb  disabledserial@a840002qcom,geni-debug-uart @@seVdefault# Bbokayi2c@a880002qcom,geni-i2c @seXdefault$ Bc okayZspi@a880002qcom,geni-spi @seXdefault% Bc  disabledi2c@a8c0002qcom,geni-i2c @seZdefault& Bd  disabledspi@a8c0002qcom,geni-spi @seZdefault' Bd  disabledi2c@a900002qcom,geni-i2c @se\default( Be  disabledspi@a900002qcom,geni-spi @se\default) Be  disabledi2c@a940002qcom,geni-i2c @@se^default* Bf  disabledspi@a940002qcom,geni-spi @@se^default+ Bf  disabledi2c@a980002qcom,geni-i2c @se`default, Bg  disabledspi@a980002qcom,geni-spi @se`default- Bg  disabledi2c@a9c0002qcom,geni-i2c @sebdefault. Bh  disabledspi@a9c0002qcom,geni-spi @sebdefault/ Bh  disabledsyscon@1f400002syscon  pinctrl@34000002qcom,sdm845-pinctrl @ B ,=Qqup-i2c0-defaultpinmux Rgpio0gpio1Wqup0qup-i2c1-defaultpinmuxRgpio17gpio18Wqup1qup-i2c2-defaultpinmuxRgpio27gpio28Wqup2qup-i2c3-defaultpinmuxRgpio41gpio42Wqup3qup-i2c4-defaultpinmuxRgpio89gpio90Wqup4qup-i2c5-defaultpinmuxRgpio85gpio86Wqup5qup-i2c6-defaultpinmuxRgpio45gpio46Wqup6qup-i2c7-defaultpinmuxRgpio93gpio94Wqup7qup-i2c8-defaultpinmuxRgpio65gpio66Wqup8qup-i2c9-default!pinmux Rgpio6gpio7Wqup9qup-i2c10-default$pinmuxRgpio55gpio56Wqup10pinconfRgpio55gpio56`oqup-i2c11-default&pinmuxRgpio31gpio32Wqup11qup-i2c12-default(pinmuxRgpio49gpio50Wqup12qup-i2c13-default*pinmuxRgpio105gpio106Wqup13qup-i2c14-default,pinmuxRgpio33gpio34Wqup14qup-i2c15-default.pinmuxRgpio81gpio82Wqup15qup-spi0-defaultpinmuxRgpio0gpio1gpio2gpio3Wqup0qup-spi1-defaultpinmuxRgpio17gpio18gpio19gpio20Wqup1qup-spi2-defaultpinmuxRgpio27gpio28gpio29gpio30Wqup2qup-spi3-defaultpinmuxRgpio41gpio42gpio43gpio44Wqup3qup-spi4-defaultpinmuxRgpio89gpio90gpio91gpio92Wqup4qup-spi5-defaultpinmuxRgpio85gpio86gpio87gpio88Wqup5qup-spi6-defaultpinmuxRgpio45gpio46gpio47gpio48Wqup6qup-spi7-defaultpinmuxRgpio93gpio94gpio95gpio96Wqup7qup-spi8-default pinmuxRgpio65gpio66gpio67gpio68Wqup8qup-spi9-default"pinmuxRgpio6gpio7gpio4gpio5Wqup9qup-spi10-default%pinmuxRgpio55gpio56gpio53gpio54Wqup10qup-spi11-default'pinmuxRgpio31gpio32gpio33gpio34Wqup11qup-spi12-default)pinmuxRgpio49gpio50gpio51gpio52Wqup12qup-spi13-default+pinmux Rgpio105gpio106gpio107gpio108Wqup13qup-spi14-default-pinmuxRgpio33gpio34gpio31gpio32Wqup14qup-spi15-default/pinmuxRgpio81gpio82gpio83gpio84Wqup15qup-uart9-default#pinmux Rgpio4gpio5Wqup9pinconf-txRgpio4`opinconf-rxRgpio5`|thermal-sensor@c263000 2qcom,sdm845-tsensqcom,tsens-v2 &0 "  thermal-sensor@c265000 2qcom,sdm845-tsensqcom,tsens-v2 &P "0spmi@c4400002qcom,spmi-pmic-arb( D ``p @`corechnlsobsrvrintrcnfg periph_irq B ,mailbox@179900002qcom,sdm845-apss-shared rsc@179c0000 apps_rsc2qcom,rpmh-rsc drv-0drv-1drv-2$B   clock-controller2qcom,sdm845-rpmh-clkMinterrupt-controller@17a00000 2arm,gic-v3  ,  B gic-its@17a400002arm,gic-v3-its%4  disabledtimer@17c90000  2arm,armv7-timer-mem frame@17ca0000?B frame@17cc0000? B  disabledframe@17cd0000? B   disabledframe@17ce0000? B   disabledframe@17cf0000? B   disabledframe@17d00000? B   disabledframe@17d10000? B   disabled interrupt-parent#address-cells#size-cellsmodelcompatiblei2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8i2c9i2c10i2c11i2c12i2c13i2c14i2c15spi0spi1spi2spi3spi4spi5spi6spi7spi8spi9spi10spi11spi12spi13spi14spi15serial0stdout-pathdevice_typeregrangesno-mapphandleenable-methodnext-level-cacheinterrupts#clock-cellsclock-frequencyclock-output-namessyscon#hwlock-cellsmemory-regionhwlocks#reset-cells#power-domain-cellsclock-namesclocksstatuspinctrl-namespinctrl-0gpio-controller#gpio-cellsinterrupt-controller#interrupt-cellsgpio-reserved-rangespinsfunctiondrive-strengthbias-disablebias-pull-up#qcom,sensors#thermal-sensor-cellsreg-namesinterrupt-namesqcom,eeqcom,channelcell-index#mbox-cellslabelqcom,tcs-offsetqcom,drv-idqcom,tcs-configmsi-controller#msi-cellsframe-number