Ƌ8((ti,am3517-craneboardti,am3517ti,omap3 +#7TI AM3517 CraneBoard (TMDSEVM3517)chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000s/ocp@68000000/serial@4809e000{/ocp@68000000/can@5c050000cpus+cpu@0arm,cortex-a8cpucpupmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2iva disableddsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+&pinmux_tps_pinsCWscm_conf@270sysconsimple-busp0+ p0Wpbias_regulator@2b0ti,pbias-omap3ti,pbias-omap_pbias_mmc_omap2430fpbias_mmc_omap2430uw@-Wclocks+mcbsp5_mux_fck@68ti,composite-mux-clockhWmcbsp5_fckti,composite-clockWmcbsp1_mux_fck@4ti,composite-mux-clockW mcbsp1_fckti,composite-clock Wmcbsp2_mux_fck@4ti,composite-mux-clock W mcbsp2_fckti,composite-clock Wmcbsp3_mux_fck@68ti,composite-mux-clock hWmcbsp3_fckti,composite-clock Wmcbsp4_mux_fck@68ti,composite-mux-clock hWmcbsp4_fckti,composite-clockWemac_ick@32cti,am35xx-gate-clock,Wxemac_fck@32cti,gate-clock, Wvpfe_ick@32cti,am35xx-gate-clock,Wyvpfe_fck@32cti,gate-clock, hsotgusb_ick_am35xx@32cti,am35xx-gate-clock,Wzhsotgusb_fck_am35xx@32cti,gate-clock,W{hecc_ck@32cti,am35xx-gate-clock,W|clockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+&aes@480c5000 ti,omap3-aesaesH PPABtxrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockYWosc_sys_ck@d40 ti,mux-clock @Wsys_ck@1270ti,divider-clockpWsys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clock dpll3_m2x2_ckfixed-factor-clock W dpll4_x2_ckfixed-factor-clock corex2_fckfixed-factor-clock  W!wkup_l4_ickfixed-factor-clock WPcorex2_d3_fckfixed-factor-clock! Wqcorex2_d5_fckfixed-factor-clock! Wrclockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockWBvirt_12m_ck fixed-clockWvirt_13m_ck fixed-clock]@Wvirt_19200000_ck fixed-clock$Wvirt_26000000_ck fixed-clockWvirt_38_4m_ck fixed-clockIWdpll4_ck@d00ti,omap3-dpll-per-clock D 0Wdpll4_m2_ck@d48ti,divider-clock? HW"dpll4_m2x2_mul_ckfixed-factor-clock" W#dpll4_m2x2_ck@d00ti,gate-clock# W$omap_96m_alwon_fckfixed-factor-clock$ W+dpll3_ck@d00ti,omap3-dpll-core-clock @ 0Wdpll3_m3_ck@1140ti,divider-clock@W%dpll3_m3x2_mul_ckfixed-factor-clock% W&dpll3_m3x2_ck@d00ti,gate-clock&  W'emu_core_alwon_ckfixed-factor-clock' Wdsys_altclk fixed-clockW0mcbsp_clks fixed-clockWdpll3_m2_ck@d40ti,divider-clock @Wcore_ckfixed-factor-clock W(dpll1_fck@940ti,divider-clock( @W)dpll1_ck@904ti,omap3-dpll-clock)  $ @ 4Wdpll1_x2_ckfixed-factor-clock W*dpll1_x2m2_ck@944ti,divider-clock* DW>cm_96m_fckfixed-factor-clock+ W,omap_96m_fck@d40 ti,mux-clock, @WGdpll4_m3_ck@e40ti,divider-clock @W-dpll4_m3x2_mul_ckfixed-factor-clock- W.dpll4_m3x2_ck@d00ti,gate-clock. W/omap_54m_fck@d40 ti,mux-clock/0 @W:cm_96m_d2_fckfixed-factor-clock, W1omap_48m_fck@d40 ti,mux-clock10 @W2omap_12m_fckfixed-factor-clock2 WIdpll4_m4_ck@e40ti,divider-clock @W3dpll4_m4x2_mul_ckti,fixed-factor-clock3+9FW4dpll4_m4x2_ck@d00ti,gate-clock4 FWvdpll4_m5_ck@f40ti,divider-clock?@W5dpll4_m5x2_mul_ckti,fixed-factor-clock5+9FW6dpll4_m5x2_ck@d00ti,gate-clock6 Fdpll4_m6_ck@1140ti,divider-clock?@W7dpll4_m6x2_mul_ckfixed-factor-clock7 W8dpll4_m6x2_ck@d00ti,gate-clock8 W9emu_per_alwon_ckfixed-factor-clock9 Weclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock( pW;clkout2_src_mux_ck@d70ti,composite-mux-clock(,: pW<clkout2_src_ckti,composite-clock;<W=sys_clkout2@d70ti,divider-clock=@ pYmpu_ckfixed-factor-clock> W?arm_fck@924ti,divider-clock? $emu_mpu_alwon_ckfixed-factor-clock? Wfl3_ick@a40ti,divider-clock( @W@l4_ick@a40ti,divider-clock@ @WArm_ick@c40ti,divider-clockA @gpt10_gate_fck@a00ti,composite-gate-clock  WCgpt10_mux_fck@a40ti,composite-mux-clockB @WDgpt10_fckti,composite-clockCDgpt11_gate_fck@a00ti,composite-gate-clock  WEgpt11_mux_fck@a40ti,composite-mux-clockB @WFgpt11_fckti,composite-clockEFcore_96m_fckfixed-factor-clockG Wmmchs2_fck@a00ti,wait-gate-clock Wmmchs1_fck@a00ti,wait-gate-clock Wi2c3_fck@a00ti,wait-gate-clock Wi2c2_fck@a00ti,wait-gate-clock Wi2c1_fck@a00ti,wait-gate-clock Wmcbsp5_gate_fck@a00ti,composite-gate-clock  Wmcbsp1_gate_fck@a00ti,composite-gate-clock  Wcore_48m_fckfixed-factor-clock2 WHmcspi4_fck@a00ti,wait-gate-clockH Wmcspi3_fck@a00ti,wait-gate-clockH Wmcspi2_fck@a00ti,wait-gate-clockH Wmcspi1_fck@a00ti,wait-gate-clockH Wuart2_fck@a00ti,wait-gate-clockH Wuart1_fck@a00ti,wait-gate-clockH  Wcore_12m_fckfixed-factor-clockI WJhdq_fck@a00ti,wait-gate-clockJ Wcore_l3_ickfixed-factor-clock@ WKsdrc_ick@a10ti,wait-gate-clockK Wwgpmc_fckfixed-factor-clockK core_l4_ickfixed-factor-clockA WLmmchs2_ick@a10ti,omap3-interface-clockL Wmmchs1_ick@a10ti,omap3-interface-clockL Whdq_ick@a10ti,omap3-interface-clockL Wmcspi4_ick@a10ti,omap3-interface-clockL Wmcspi3_ick@a10ti,omap3-interface-clockL Wmcspi2_ick@a10ti,omap3-interface-clockL Wmcspi1_ick@a10ti,omap3-interface-clockL Wi2c3_ick@a10ti,omap3-interface-clockL Wi2c2_ick@a10ti,omap3-interface-clockL Wi2c1_ick@a10ti,omap3-interface-clockL Wuart2_ick@a10ti,omap3-interface-clockL Wuart1_ick@a10ti,omap3-interface-clockL  Wgpt11_ick@a10ti,omap3-interface-clockL  Wgpt10_ick@a10ti,omap3-interface-clockL  Wmcbsp5_ick@a10ti,omap3-interface-clockL  Wmcbsp1_ick@a10ti,omap3-interface-clockL  Womapctrl_ick@a10ti,omap3-interface-clockL Wdss_tv_fck@e00ti,gate-clock:Wdss_96m_fck@e00ti,gate-clockGWdss2_alwon_fck@e00ti,gate-clockWdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock WMgpt1_mux_fck@c40ti,composite-mux-clockB @WNgpt1_fckti,composite-clockMNaes2_ick@a10ti,omap3-interface-clockL Wwkup_32k_fckfixed-factor-clockB WOgpio1_dbck@c00ti,gate-clockO Wsha12_ick@a10ti,omap3-interface-clockL Wwdt2_fck@c00ti,wait-gate-clockO Wwdt2_ick@c10ti,omap3-interface-clockP Wwdt1_ick@c10ti,omap3-interface-clockP Wgpio1_ick@c10ti,omap3-interface-clockP Womap_32ksync_ick@c10ti,omap3-interface-clockP Wgpt12_ick@c10ti,omap3-interface-clockP Wgpt1_ick@c10ti,omap3-interface-clockP Wper_96m_fckfixed-factor-clock+ W per_48m_fckfixed-factor-clock2 WQuart3_fck@1000ti,wait-gate-clockQ W}gpt2_gate_fck@1000ti,composite-gate-clockWRgpt2_mux_fck@1040ti,composite-mux-clockB@WSgpt2_fckti,composite-clockRSgpt3_gate_fck@1000ti,composite-gate-clockWTgpt3_mux_fck@1040ti,composite-mux-clockB@WUgpt3_fckti,composite-clockTUgpt4_gate_fck@1000ti,composite-gate-clockWVgpt4_mux_fck@1040ti,composite-mux-clockB@WWgpt4_fckti,composite-clockVWgpt5_gate_fck@1000ti,composite-gate-clockWXgpt5_mux_fck@1040ti,composite-mux-clockB@WYgpt5_fckti,composite-clockXYgpt6_gate_fck@1000ti,composite-gate-clockWZgpt6_mux_fck@1040ti,composite-mux-clockB@W[gpt6_fckti,composite-clockZ[gpt7_gate_fck@1000ti,composite-gate-clockW\gpt7_mux_fck@1040ti,composite-mux-clockB@W]gpt7_fckti,composite-clock\]gpt8_gate_fck@1000ti,composite-gate-clock W^gpt8_mux_fck@1040ti,composite-mux-clockB@W_gpt8_fckti,composite-clock^_gpt9_gate_fck@1000ti,composite-gate-clock W`gpt9_mux_fck@1040ti,composite-mux-clockB@Wagpt9_fckti,composite-clock`aper_32k_alwon_fckfixed-factor-clockB Wbgpio6_dbck@1000ti,gate-clockbW~gpio5_dbck@1000ti,gate-clockbWgpio4_dbck@1000ti,gate-clockbWgpio3_dbck@1000ti,gate-clockbWgpio2_dbck@1000ti,gate-clockb Wwdt3_fck@1000ti,wait-gate-clockb Wper_l4_ickfixed-factor-clockA Wcgpio6_ick@1010ti,omap3-interface-clockcWgpio5_ick@1010ti,omap3-interface-clockcWgpio4_ick@1010ti,omap3-interface-clockcWgpio3_ick@1010ti,omap3-interface-clockcWgpio2_ick@1010ti,omap3-interface-clockc Wwdt3_ick@1010ti,omap3-interface-clockc Wuart3_ick@1010ti,omap3-interface-clockc Wuart4_ick@1010ti,omap3-interface-clockcWgpt9_ick@1010ti,omap3-interface-clockc Wgpt8_ick@1010ti,omap3-interface-clockc Wgpt7_ick@1010ti,omap3-interface-clockcWgpt6_ick@1010ti,omap3-interface-clockcWgpt5_ick@1010ti,omap3-interface-clockcWgpt4_ick@1010ti,omap3-interface-clockcWgpt3_ick@1010ti,omap3-interface-clockcWgpt2_ick@1010ti,omap3-interface-clockcWmcbsp2_ick@1010ti,omap3-interface-clockcWmcbsp3_ick@1010ti,omap3-interface-clockcWmcbsp4_ick@1010ti,omap3-interface-clockcWmcbsp2_gate_fck@1000ti,composite-gate-clockW mcbsp3_gate_fck@1000ti,composite-gate-clockW mcbsp4_gate_fck@1000ti,composite-gate-clockWemu_src_mux_ck@1140 ti,mux-clockdef@Wgemu_src_ckti,clkdm-gate-clockgWhpclk_fck@1140ti,divider-clockh@pclkx2_fck@1140ti,divider-clockh@atclk_fck@1140ti,divider-clockh@traceclk_src_fck@1140 ti,mux-clockdef@Witraceclk_fck@1140ti,divider-clocki @secure_32k_fck fixed-clockWjgpt12_fckfixed-factor-clockj wdt1_fckfixed-factor-clockj ipss_ick@a10ti,am35xx-interface-clockK Wrmii_ck fixed-clockWpclk_ck fixed-clockWuart4_ick_am35xx@a10ti,omap3-interface-clockL uart4_fck_am35xx@a00ti,wait-gate-clockH dpll5_ck@d04ti,omap3-dpll-clock  $ L 4oWkdpll5_m2_ck@d50ti,divider-clockk PWusgx_gate_fck@b00ti,composite-gate-clock( Wscore_d3_ckfixed-factor-clock( Wlcore_d4_ckfixed-factor-clock( Wmcore_d6_ckfixed-factor-clock( Wnomap_192m_alwon_fckfixed-factor-clock$ Wocore_d2_ckfixed-factor-clock( Wpsgx_mux_fck@b40ti,composite-mux-clock lmn,opqr @Wtsgx_fckti,composite-clockstsgx_ick@b10ti,wait-gate-clock@ Wcpefuse_fck@a08ti,gate-clock Wts_fck@a08ti,gate-clockB Wusbtll_fck@a08ti,wait-gate-clocku Wusbtll_ick@a18ti,omap3-interface-clockL Wmmchs3_ick@a10ti,omap3-interface-clockL Wmmchs3_fck@a00ti,wait-gate-clock Wdss1_alwon_fck_3430es2@e00ti,dss-gate-clockvFWdss_ick_3430es2@e10ti,omap3-dss-interface-clockAWusbhost_120m_fck@1400ti,gate-clockuWusbhost_48m_fck@1400ti,dss-gate-clock2Wusbhost_ick@1410ti,omap3-dss-interface-clockAWclockdomainscore_l3_clkdmti,clockdomainwxyz{|dpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainh}~emu_clkdmti,clockdomainhdpll4_clkdmti,clockdomainwkup_clkdmti,clockdomain dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaindpll5_clkdmti,clockdomainksgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain counter@48320000ti,omap-counter32kH2  counter_32kinterrupt-controller@48200000ti,omap3-intcH Wdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaH`  `dmaWgpio@48310000ti,omap3-gpioH1gpio1gpio@49050000ti,omap3-gpioIgpio2gpio@49052000ti,omap3-gpioI gpio3gpio@49054000ti,omap3-gpioI@ gpio4gpio@49056000ti,omap3-gpioI`!gpio5gpio@49058000ti,omap3-gpioI"gpio6serial@4806a000ti,omap3-uartH H12txrxuart1lserial@4806c000ti,omap3-uartHI34txrxuart2lserial@49020000ti,omap3-uartIJ56txrxuart3li2c@48070000 ti,omap3-i2cH8txrx+i2c1'@tps@2d- ti,tps65910default %1=IUamregulators+regulator@0zvrtcregulator@1zvioregulator@2zvdd1 fvdd_coreuOOregulator@3zvdd2fvdd_shvu2Z2ZWregulator@4zvdd3regulator@5zvdig1regulator@6zvdig2regulator@7zvplluw@w@regulator@8zvdacuw@w@regulator@9 zvaux1uw@w@regulator@10 zvaux2uw@w@regulator@11 zvaux33regulator@12 zvmmcu2Z2Zregulator@13 zvbbi2c@48072000 ti,omap3-i2cH 9txrx+i2c2 disabledi2c@48060000 ti,omap3-i2cH=txrx+i2c3 disabledmailbox@48094000ti,omap3-mailboxmailboxH @ disableddsp  spi@48098000ti,omap2-mcspiH A+mcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspiH B+mcspi2 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [+mcspi3 tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0+mcspi4FGtx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1 =>txrx#/mmc@480b4000ti,omap3-hsmmcH @Vmmc2/0txrx disabledmmc@480ad000ti,omap3-hsmmcH ^mmc3MNtxrx disabledmmu@480bd4009ti,omap2-iommuH mmu_ispF disabledmmu@5d0000009ti,omap2-iommu]mmu_iva disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@Vmpu ;< `commontxrxpmcbsp1 txrxfck disabledmcbsp@49022000ti,omap3-mcbspI I Vmpusidetone>?`commontxrxsidetonepmcbsp2mcbsp2_sidetone!"txrxfckick disabledmcbsp@49024000ti,omap3-mcbspI@I VmpusidetoneYZ`commontxrxsidetonepmcbsp3mcbsp3_sidetonetxrxfckick disabledmcbsp@49026000ti,omap3-mcbspI`Vmpu 67 `commontxrxpmcbsp4txrxfck disabledmcbsp@48096000ti,omap3-mcbspH `Vmpu QR `commontxrxpmcbsp5txrxfck disabledsham@480c3000ti,omap3-shamshamH 0d1Erxtimer@48318000ti,omap3430-timerH1%timer1timer@49032000ti,omap3430-timerI &timer2timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8timer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11timer@48304000ti,omap3430-timerH0@_timer12usbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs+ohci@48064400ti,ohci-omap3HDLehci@48064800 ti,ehci-omapHHMgpmc@6e000000ti,omap3430-gpmcgpmcnrxtx+usb_otg_hs@480ab000ti,omap3-musbH \]`mcdma usb_otg_hs   disableddss@48050000 ti,omap3-dssH disabled dss_corefck+dispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H Vprotophypll disabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbiH disabled dss_rfbifckickencoder@48050c00ti,omap3-vencH  disabled dss_vencfckssi-controller@48058000 ti,omap3-ssissi disabledHHVsysgddG`gdd_mpu+ssi-port@4805a000ti,omap3-ssi-portHHVtxrxCDssi-port@4805b000ti,omap3-ssi-portHHVtxrxEFam35x_otg_hs@5c040000ti,omap3-musb am35x_otg_hs disabled\G`mcethernet@5c000000ti,am3517-emac davinci_emacokay\CDEF_6Up xickethernet@5c030000ti,davinci_mdio davinci_mdiookay\B@+fckserial@4809e000ti,omap3-uartuart4 disabledH T76txrxlpinmux@480025d8 ti,omap3-padconfpinctrl-singleH%$+&can@5c050000ti,am3517-hecc disabled\\0\ Vhecchecc-rammbx|memory@80000000memoryfixedregulatorregulator-fixedfvbatuLK@LK@W compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2serial3candevice_typeregclocksclock-namesclock-latencyinterruptsti,hwmodsstatusranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lock#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0ti,en-ck32k-xtalvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-compatibleregulator-always-onregulator-boot-on#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplybus-width#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-size#sound-dai-cellsti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureremote-wakeup-connectedgpmc,num-csgpmc,num-waitpinsmultipointnum-epsram-bitsti,davinci-ctrl-reg-offsetti,davinci-ctrl-mod-reg-offsetti,davinci-ctrl-ram-offsetti,davinci-ctrl-ram-sizeti,davinci-rmii-enlocal-mac-addressbus_freq