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#address-cells#size-cellsmodelcompatiblestdout-pathgpio0gpio1serial0serial1device_typereginterrupts-extendedcontrollerinterrupt-parentpcie-mem-aperturepcie-io-aperturerangesclocksstatuscache-unifiedcache-levelarm,double-linefill-incrarm,double-linefill-wraparm,double-linefillprefetch-datainterrupts#interrupt-cellsinterrupt-controllerphandletimeout-mspinctrl-namespinctrl-0clock-frequencygpio-controller#gpio-cellsreg-shiftreg-io-widthmarvell,pinsmarvell,functionreg-namesngpios#pwm-cells#clock-cellsmsi-controllerclock-namestx-csum-limitphyphy-modebuffer-managerbm,pool-longbm,pool-shortvcc-supplydmacap,memcpydmacap,xordmacap,memsetmarvell,crypto-sramsmarvell,crypto-sram-sizetarget-supplyinternal-memclock-output-namesmrvl,clk-delay-cyclesno-1-8-vbroken-cdwp-invertedbus-widthusb-phyno-memory-wccell-indexspi-max-frequencym25p,fast-readmsi-parentbus-rangeassigned-addressesinterrupt-map-maskinterrupt-mapmarvell,pcie-portmarvell,pcie-lanegpio-fan,speed-mapenable-method#phy-cellsregulator-nameregulator-min-microvoltregulator-max-microvoltenable-active-highgpioregulator-always-onregulator-boot-onvin-supply