>D80(,/ti,dra76-evmti,dra762ti,dra7&7TI DRA762 EVMchosen=/ocp/serial@4806a000aliasesI/ocp/i2c@48070000N/ocp/i2c@48072000S/ocp/i2c@48060000X/ocp/i2c@4807a000]/ocp/i2c@4807c000b/ocp/serial@4806a000j/ocp/serial@4806c000r/ocp/serial@48020000z/ocp/serial@4806e000/ocp/serial@48066000/ocp/serial@48068000/ocp/serial@48420000/ocp/serial@48422000/ocp/serial@48424000/ocp/serial@4ae2b000&/ocp/ethernet@48484000/slave@48480200&/ocp/ethernet@48484000/slave@48480300/ocp/can@4ae3c000/ocp/can@48480000/ocp/spi@4b300000timerarm,armv7-timer disabled0   &interrupt-controller@48211000arm,cortex-a15-gic@H!H! H!@ H!`   &interrupt-controller@48281000&ti,omap5-wugen-mputi,omap4-wugen-mpuH(&cpuscpu@0cpuarm,cortex-a15)=DcpuP^mxcpu@1cpuarm,cortex-a15)=DcpuP^mopp-tableoperating-points-v2-ti-cpuopp_nom-1000000000;, P0, P0opp_od-1176000000FV@ @@ @opp_high@1500000000Yh/v~v~socti,omap-inframpu ti,omap5-mpumpuocpti,dra7-l3-nocsimple-bus؀l3_main_1l3_main_2 DE  l4@4a000000ti,dra7-l4-cfgsimple-bus J"scm@2000ti,dra7-scm-coresimple-bus   scm_conf@0sysconsimple-bus  pbias_regulator@e00ti,pbias-dra7ti,pbias-omap pbias_mmc_omap5pbias_mmc_omap5w@2Zclocksdss_deshdcp_clk@5586ti,gate-clock= CXehrpwm0_tbclk@5586ti,gate-clock= CXehrpwm1_tbclk@5586ti,gate-clock= CXehrpwm2_tbclk@5586ti,gate-clock= CXsys_32k_ck6 ti,mux-clock= CRdpll_gmac_h14x2_ctrl_ck@3fc6ti,divider-clock=P?C[hxĴdpll_gmac_h14x2_ctrl_mux_ck@3fc6 ti,mux-clock=C[hmcan_clk@3fc6ti,gate-clock=Cpinmux@1400ti,dra7-padconfpinctrl-singleh ?mmc1_pins_default0TX\`dhmmc1_pins_hs0TX\`dhmmc1_pins_sdr500TX\`dhmmc1_pins_ddr500TX\`dhmmc2_pins_defaultPmmc2_pins_hs200Pmmc3_pins_default0|mmc4_pins_hs0scm_conf@1c04syscon scm_conf@1c24syscon$$dma-router@b78ti,dra7-dma-crossbar x(8dma-router@c78ti,dra7-dma-crossbar x|(8cm_core_aon@5000ti,dra7-cm-core-aonsimple-busP  P clocksatl_clkin0_ck6ti,dra7-atl-clock =atl_clkin1_ck6ti,dra7-atl-clock =atl_clkin2_ck6ti,dra7-atl-clock =atl_clkin3_ck6ti,dra7-atl-clock =hdmi_clkin_ck6 fixed-clockD3mlb_clkin_ck6 fixed-clockDmlbp_clkin_ck6 fixed-clockDpciesref_acs_clk_ck6 fixed-clockDBref_clkin0_ck6 fixed-clockDref_clkin1_ck6 fixed-clockDref_clkin2_ck6 fixed-clockDref_clkin3_ck6 fixed-clockDrmii_clk_ck6 fixed-clockDsdvenc_clkin_ck6 fixed-clockDsecure_32k_clk_src_ck6 fixed-clockDmsys_clk32_crystal_ck6 fixed-clockD sys_clk32_pseudo_ck6fixed-factor-clock=T_b virt_12000000_ck6 fixed-clockD[virt_13000000_ck6 fixed-clockD]@virt_16800000_ck6 fixed-clockDY]virt_19200000_ck6 fixed-clockD$^virt_20000000_ck6 fixed-clockD1-\virt_26000000_ck6 fixed-clockD_virt_27000000_ck6 fixed-clockD`virt_38400000_ck6 fixed-clockDIasys_clkin26 fixed-clockDXbusb_otg_clkin_ck6 fixed-clockDjvideo1_clkin_ck6 fixed-clockD<video1_m2_clkin_ck6 fixed-clockD2video2_clkin_ck6 fixed-clockD=video2_m2_clkin_ck6 fixed-clockD1dpll_abe_ck@1e06ti,omap4-dpll-m4xen-clock=dpll_abe_x2_ck6ti,omap4-dpll-x2-clock=dpll_abe_m2x2_ck@1f06ti,divider-clock=Pi{abe_clk@1086ti,divider-clock=Pddpll_abe_m2_ck@1f06ti,divider-clock=Pi{fdpll_abe_m3x2_ck@1f46ti,divider-clock=Pi{dpll_core_byp_mux@12c6 ti,mux-clock=C,dpll_core_ck@1206ti,omap4-dpll-core-clock= $,(dpll_core_x2_ck6ti,omap4-dpll-x2-clock=dpll_core_h12x2_ck@13c6ti,divider-clock=P?i<{mpu_dpll_hs_clk_div6fixed-factor-clock=T_ dpll_mpu_ck@1606ti,omap5-mpu-dpll-clock= `dlhdpll_mpu_m2_ck@1706ti,divider-clock=Pip{!mpu_dclk_div6fixed-factor-clock=!T_qdsp_dpll_hs_clk_div6fixed-factor-clock=T_"dpll_dsp_byp_mux@2406 ti,mux-clock="C@#dpll_dsp_ck@2346ti,omap4-dpll-clock=#48@<h$x#F$dpll_dsp_m2_ck@2446ti,divider-clock=$PiD{h%x#F%iva_dpll_hs_clk_div6fixed-factor-clock=T_&dpll_iva_byp_mux@1ac6 ti,mux-clock=&C'dpll_iva_ck@1a06ti,omap4-dpll-clock='h(xEp}@(dpll_iva_m2_ck@1b06ti,divider-clock=(Pi{h)x%)iva_dclk6fixed-factor-clock=)T_sdpll_gpu_byp_mux@2e46 ti,mux-clock=C*dpll_gpu_ck@2d86ti,omap4-dpll-clock=*h+xLy@+dpll_gpu_m2_ck@2e86ti,divider-clock=+Pi{h,x_(k,dpll_core_m2_ck@1306ti,divider-clock=Pi0{-core_dpll_out_dclk_div6fixed-factor-clock=-T_udpll_ddr_byp_mux@21c6 ti,mux-clock=C.dpll_ddr_ck@2106ti,omap4-dpll-clock=./dpll_ddr_m2_ck@2206ti,divider-clock=/Pi {gdpll_gmac_byp_mux@2b46 ti,mux-clock=C0dpll_gmac_ck@2a86ti,omap4-dpll-clock=0dpll_gmac_m2_ck@2b86ti,divider-clock=Pi{hvideo2_dclk_div6fixed-factor-clock=1T_wvideo1_dclk_div6fixed-factor-clock=2T_xhdmi_dclk_div6fixed-factor-clock=3T_yper_dpll_hs_clk_div6fixed-factor-clock=T_Eusb_dpll_hs_clk_div6fixed-factor-clock=T_Ieve_dpll_hs_clk_div6fixed-factor-clock=T_4dpll_eve_byp_mux@2906 ti,mux-clock=4C5dpll_eve_ck@2846ti,omap4-dpll-clock=56dpll_eve_m2_ck@2946ti,divider-clock=6Pi{7eve_dclk_div6fixed-factor-clock=7T_dpll_core_h13x2_ck@1406ti,divider-clock=P?i@{dpll_core_h14x2_ck@1446ti,divider-clock=P?iD{Sdpll_core_h22x2_ck@1546ti,divider-clock=P?iT{>dpll_core_h23x2_ck@1586ti,divider-clock=P?iX{Xdpll_core_h24x2_ck@15c6ti,divider-clock=P?i\{dpll_ddr_x2_ck6ti,omap4-dpll-x2-clock=/8dpll_ddr_h11x2_ck@2286ti,divider-clock=8P?i({dpll_dsp_x2_ck6ti,omap4-dpll-x2-clock=$9dpll_dsp_m3x2_ck@2486ti,divider-clock=9PiH{h:xׄ:dpll_gmac_x2_ck6ti,omap4-dpll-x2-clock=dpll_gmac_h11x2_ck@2c06ti,divider-clock=P?i{;dpll_gmac_h12x2_ck@2c46ti,divider-clock=P?i{dpll_gmac_h13x2_ck@2c86ti,divider-clock=P?i{dpll_gmac_m3x2_ck@2bc6ti,divider-clock=Pi{gmii_m_clk_div6fixed-factor-clock=;T_hdmi_clk2_div6fixed-factor-clock=3T_hdmi_div_clk6fixed-factor-clock=3T_l3_iclk_div@1006ti,divider-clockPC= l4_root_clk_div6fixed-factor-clock= T_ video1_clk2_div6fixed-factor-clock=<T_video1_div_clk6fixed-factor-clock=<T_video2_clk2_div6fixed-factor-clock==T_video2_div_clk6fixed-factor-clock==T_ipu1_gfclk_mux@5206 ti,mux-clock=>C h?>?dummy_ck6 fixed-clockDclockdomainsmpu_cm@300 ti,omap4-cm clk@20 ti,clkctrl 6ipu_cm@500 ti,omap4-cm clk@40 ti,clkctrl@D6rtc_cm@700 ti,omap4-cm clk@40 ti,clkctrl@6cm_core@8000ti,dra7-cm-coresimple-bus0 0clocksdpll_pcie_ref_ck@2006ti,omap4-dpll-clock= @dpll_pcie_ref_m2ldo_ck@2106ti,divider-clock=@Pi{Aapll_pcie_in_clk_mux@4ae06118 ti,mux-clock=AB6CCapll_pcie_ck@21c6ti,dra7-apll-clock=C@ Doptfclk_pciephy_div@4a00821cti,divider-clock=D6CPapll_pcie_clkvcoldo6fixed-factor-clock=DT_apll_pcie_clkvcoldo_div6fixed-factor-clock=DT_apll_pcie_m2_ck6fixed-factor-clock=DT_ldpll_per_byp_mux@14c6 ti,mux-clock=ECLFdpll_per_ck@1406ti,omap4-dpll-clock=F@DLHGdpll_per_m2_ck@1506ti,divider-clock=GPiP{Hfunc_96m_aon_dclk_div6fixed-factor-clock=HT_zdpll_usb_byp_mux@18c6 ti,mux-clock=ICJdpll_usb_ck@1806ti,omap4-dpll-j-type-clock=JKdpll_usb_m2_ck@1906ti,divider-clock=KPi{Odpll_pcie_ref_m2_ck@2106ti,divider-clock=@Pi{kdpll_per_x2_ck6ti,omap4-dpll-x2-clock=GLdpll_per_h11x2_ck@1586ti,divider-clock=LP?iX{Mdpll_per_h12x2_ck@15c6ti,divider-clock=LP?i\{dpll_per_h13x2_ck@1606ti,divider-clock=LP?i`{dpll_per_h14x2_ck@1646ti,divider-clock=LP?id{Tdpll_per_m2x2_ck@1506ti,divider-clock=LPiP{Ndpll_usb_clkdcoldo6fixed-factor-clock=KT_Qfunc_128m_clk6fixed-factor-clock=MT_func_12m_fclk6fixed-factor-clock=NT_func_24m_clk6fixed-factor-clock=HT_func_48m_fclk6fixed-factor-clock=NT_func_96m_fclk6fixed-factor-clock=NT_l3init_60m_fclk@1046ti,divider-clock=Oclkout2_clk@6b06ti,gate-clock=PCl3init_960m_gfclk@6c06ti,gate-clock=QCusb_phy1_always_on_clk32k@6406ti,gate-clock=RC@usb_phy2_always_on_clk32k@6886ti,gate-clock=RCusb_phy3_always_on_clk32k@6986ti,gate-clock=RCgpu_core_gclk_mux@12206 ti,mux-clock =ST,C hU,Ugpu_hyd_gclk_mux@12206 ti,mux-clock =ST,C hV,Vl3instr_ts_gclk_div@e506ti,divider-clock=WCP  vip1_gclk_mux@10206 ti,mux-clock= XC vip2_gclk_mux@10286 ti,mux-clock= XC(vip3_gclk_mux@10306 ti,mux-clock= XC0clockdomainscoreaon_clkdmti,clockdomain=Kcoreaon_cm@600 ti,omap4-cm clk@20 ti,clkctrl 6l3main1_cm@700 ti,omap4-cm clk@20 ti,clkctrl t6dma_cm@a00 ti,omap4-cm   clk@20 ti,clkctrl 6emif_cm@b00 ti,omap4-cm   clk@20 ti,clkctrl 6atl_cm@c00 ti,omap4-cm   clk@0 ti,clkctrl6l4cfg_cm@d00 ti,omap4-cm   clk@20 ti,clkctrl 6l3instr_cm@e00 ti,omap4-cm clk@20 ti,clkctrl 6dss_cm@1100 ti,omap4-cm clk@20 ti,clkctrl 6l3init_cm@1300 ti,omap4-cm clk@20 ti,clkctrl 6l4per_cm@1700 ti,omap4-cm clk@0 ti,clkctrl 6 hYhZYl4@4ae00000ti,dra7-l4-wkupsimple-bus Jcounter@4000ti,omap-counter32k@@ counter_32kprm@6000ti,dra7-prmsimple-bus`0  `0clockssys_clkin1@1106 ti,mux-clock=[\]^_`a{abe_dpll_sys_clk_mux@1186 ti,mux-clock=bcabe_dpll_bypass_clk_mux@1146 ti,mux-clock=cRabe_dpll_clk_mux@10c6 ti,mux-clock=cR abe_24m_fclk@11c6ti,divider-clock=Zaess_fclk@1786ti,divider-clock=dxPeabe_giclk_div@1746ti,divider-clock=etPabe_lp_clk_div@1d86ti,divider-clock= abe_sys_clk_div@1206ti,divider-clock= Padc_gfclk_mux@1dc6 ti,mux-clock =bRsys_clk1_dclk_div@1c86ti,divider-clock=P@nsys_clk2_dclk_div@1cc6ti,divider-clock=bP@oper_abe_x1_dclk_div@1bc6ti,divider-clock=fP@pdsp_gclk_div@18c6ti,divider-clock=%P@rgpu_dclk@1a06ti,divider-clock=,P@temif_phy_dclk_div@1906ti,divider-clock=gP@vgmac_250m_dclk_div@19c6ti,divider-clock=hP@igmac_main_clk6fixed-factor-clock=iT_l3init_480m_dclk_div@1ac6ti,divider-clock=OP@{usb_otg_dclk_div@1846ti,divider-clock=jP@|sata_dclk_div@1c06ti,divider-clock=P@}pcie2_dclk_div@1b86ti,divider-clock=kP@~pcie_dclk_div@1b46ti,divider-clock=lP@emu_dclk_div@1946ti,divider-clock=P@secure_32k_dclk_div@1c46ti,divider-clock=mP@clkoutmux0_clk_mux@1586 ti,mux-clockX=nopqrstuviwxyz{|}~Xclkoutmux1_clk_mux@15c6 ti,mux-clockX=nopqrstuviwxyz{|}~\clkoutmux2_clk_mux@1606 ti,mux-clockX=nopqrstuviwxyz{|}~`Pcustefuse_sys_gfclk_div6fixed-factor-clock=T_eve_clk@1806 ti,mux-clock=7:hdmi_dpll_clk_mux@1646 ti,mux-clock=bdmlb_clk@1346ti,divider-clock=P@4mlbp_clk@1306ti,divider-clock=P@0per_abe_x1_gfclk2_div@1386ti,divider-clock=fP@8timer_sys_clk_div@1446ti,divider-clock=DPvideo1_dpll_clk_mux@1686 ti,mux-clock=bhvideo2_dpll_clk_mux@16c6 ti,mux-clock=blwkupaon_iclk_mux@1086 ti,mux-clock=Wclockdomainswkupaon_cm@1800 ti,omap4-cm clk@20 ti,clkctrl l6scm_conf@c000sysconaxi@0 simple-busQQ0 pcie@51000000Q Q L rc_dbicsti_confconfigpci0с0 00pcie1pcie-phy0pcie-phy1 ` *okayti,dra746-pcie-rcti,dra7-pcieinterrupt-controllerpcie_ep@51000000 Q(Q LQ(&ep_dbicsti_confep_dbics2addr_space ETpcie1pcie-phy0pcie-phy1 * disabled"ti,dra746-pcie-epti,dra7-pcie-epaxi@1 simple-busQQ00 disabledpcie@51800000Q Q L rc_dbicsti_confconfigcdpci0с0000pcie2 pcie-phy0 ` *ti,dra746-pcie-rcti,dra7-pcieinterrupt-controllerocmcram@40300000 mmio-sram@0 @0sram-hs@0ti,secure-ramocmcram@40400000 disabled mmio-sram@@ @@ocmcram@40500000 disabled mmio-sram@P @Pbandgap@4a0021e00J! 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