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disabledsdma@63fb0000!fsl,imx53-sdmafsl,imx35-sdmac@8ipgahbsdma-imx53.binj cspi@63fc0000!fsl,imx53-cspifsl,imx35-cspic@&77ipgper disabledi2c@63fc4000!fsl,imx53-i2cfsl,imx21-i2cc@@?# disabledi2c@63fc8000!fsl,imx53-i2cfsl,imx21-i2cc@>"okay  defaultgpio*    ds1339@68!dallas,ds1339h default+,5Kssi@63fcc000^*!fsl,imx53-ssifsl,imx51-ssifsl,imx21-ssic@0 ipgbaud $  )rxtxookayj;audmux@63fd0000"!fsl,imx53-audmuxfsl,imx31-audmuxc@okay default-nand@63fdb000!fsl,imx53-nandc<okay default.aphw~ssi@63fe8000^*!fsl,imx53-ssifsl,imx51-ssifsl,imx21-ssic@`2 ipgbaud $ . /)rxtxo disabledethernet@63fec000!fsl,imx53-fecfsl,imx25-fecc@W*** ipgahbptpokay default/rmii 01mdioethernet-phy@0 ethernet-phyj1tve@63ff0000!fsl,imx53-tvec\Et tvedi_sel disabledportendpoint2jvpu@63ff4000!fsl,imx53-vpucnm,coda7541c@ @?perahb3crypto@63ff8000!fsl,imx53-saharac@ipgahbsram@f8000000 !mmio-sramj3memory@70000000memorypclock-mclk !fixed-clockrj)gpio-keys !gpio-keys default4power Power Button 5tleds !gpio-leds default6user Heartbeat  heartbeatregulator-2v5!regulator-fixed2V5 &%!&%j'regulator-3v3!regulator-fixed3V3 2Z!2Zj(regulator-can-xcvr!regulator-fixed CAN XCVR 2Z!2Z default7 9,j#regulator-usbh1-vbus!regulator-fixed usbh1_vbus LK@!LK@ default8 9 >jregulator-usbotg-vbus!regulator-fixed usbotg_vbus LK@!LK@ default9 9:>jsound0!karo,tx53-audio-sgtl5000fsl,imx-audio-sgtl5000tx53-audio-sgtl5000Q;`<8lMIC_INMic JackMic JackMic BiasHeadphone JackHP_OUTzbacklight0!pwm-backlight= (  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcd2backlight1!pwm-backlight> (  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcd2regulator-lvds0-pwr!regulator-fixed LVDS0 POWER 2Z!2Z 9 >regulator-lvds1-pwr!regulator-fixed LVDS1 POWER 2Z!2Z 9> #address-cells#size-cellsmodelcompatibleethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6i2c0i2c1i2c2mmc0mmc1mmc2mmc3serial0serial1serial2serial3serial4spi0spi1spi2can0can1ipureg-can-xcvrusbh1usbotgdisplaylvds0lvds1device_typeregclocksclock-latencyvoltage-toleranceoperating-pointsportsinterrupt-controller#interrupt-cellsphandle#clock-cellsclock-frequencyinterrupt-parentinterruptsclock-names#phy-cellsstatusrangesresetsremote-endpointbus-widthcd-gpiosfsl,wp-controllerpinctrl-namespinctrl-0dmasdma-namesuart-has-rtsctscs-gpiosspi-max-frequency#sound-dai-cellsfsl,fifo-depthfsl,usbmiscfsl,usbphyphy_typedr_modedisable-over-currentvbus-supply#index-cellsgpio-controller#gpio-cellsfsl,pinsgprfsl,data-mappingfsl,data-widthnative-modehactivevactivehback-porchhsync-lenhfront-porchvback-porchvsync-lenvfront-porchhsync-activevsync-activede-activepixelclk-active#pwm-cellsxceiver-supply#reset-cellspinctrl-1scl-gpiossda-gpiosVDDA-supplyVDDIO-supply#dma-cellsfsl,sdma-ram-script-nametrickle-resistor-ohmstrickle-diode-disablenand-bus-widthnand-ecc-modenand-on-flash-bbtphy-modephy-reset-gpiosphy-handlemac-addressiramlabellinux,codewakeup-sourcelinux,default-triggerregulator-nameregulator-min-microvoltregulator-max-microvoltgpioenable-active-highssi-controlleraudio-codecaudio-routingmux-int-portmux-ext-portpwmspower-supplybrightness-levelsdefault-brightness-levelregulator-boot-on