╨ ■эЧ<8П╘(hПЬ)Liebherr (LWN) display5 i.MX6 Quad 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#address-cells#size-cellsmodelcompatibledevice_typeethernet0can0can1gpio0gpio1gpio2gpio3gpio4gpio5gpio6i2c0i2c1i2c2ipu0mmc0mmc1mmc2mmc3serial0serial1serial2serial3serial4spi0spi1spi2spi3usbphy0usbphy1ipu1spi4#clock-cellsclock-frequencyinterrupt-parentinterruptsfsl,tempmonfsl,tempmon-dataclocksgprstatusclock-namesregfsl,data-mappingfsl,data-widthremote-endpointphandlerangesinterrupt-names#dma-cellsdma-channelsreg-namesdmasdma-namespower-domains#interrupt-cellsinterrupt-controllercache-unifiedcache-levelarm,tag-latencyarm,data-latencyarm,shared-overridebus-rangenum-lanesinterrupt-map-maskinterrupt-mapcs-gpiospinctrl-namespinctrl-0spi-max-frequencylabelread-only#sound-dai-cellsfsl,fifo-depthfsl,asrc-ratefsl,asrc-widthresetsiram#pwm-cellsgpio-controller#gpio-cellsgpio-rangesregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onanatop-reg-offsetanatop-vol-bit-shiftanatop-vol-bit-widthanatop-min-bit-valanatop-min-voltageanatop-max-voltageanatop-enable-bitanatop-delay-reg-offsetanatop-delay-bit-shiftanatop-delay-bit-widthregulator-enable-ramp-delayfsl,anatopregmapvalue#reset-cells#power-domain-cellspower-supply#mux-control-cellsmux-reg-masksmux-controlsfsl,pinsfsl,sdma-ram-script-namefsl,usbphyfsl,usbmiscahb-burst-configtx-burst-size-dwordrx-burst-size-dworddr_modevbus-supply#index-cellsphy-handlephy-modemarvell,reg-initmax-speedbus-widthnon-removablepagesizeregulator-boot-onregulator-ramp-delayfsl,weim-cs-gprfsl,audmux-portfsl,port-configuart-has-rtsctsnext-level-cacheoperating-pointsfsl,soc-operating-pointsclock-latency#cooling-cellsarm-supplypu-supplysoc-supplyportspwmsbrightness-levelsdefault-brightness-levelenable-gpiosgpioenable-active-highformatbitclock-masterframe-mastersound-daibacklight