$8(LIheadacoustics,omap3-ha-lcdtechnexion,omap3-tao3530ti,omap34xxti,omap3 +77TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOMchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000 s/displaycpus+cpu@0arm,cortex-a8|cpucpu(HАg8 Odp` 'ppmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+9Vdefault d pinmux_hsusbb2_pins`n          pinmux_mmc1_pinsPn "$&pinmux_mmc2_pins0n(*,.02pinmux_wlan_gpion^pinmux_uart3_pinsnnAppinmux_i2c3_pinsnpinmux_mcspi1_pins npinmux_mcspi3_pins npinmux_mcbsp3_pins n<>@Bpinmux_twl4030_pinsnApinmux_sound2_pinsnnpinmux_led_blue_pinsnpinmux_led_green_pinsn pinmux_led_red_pinsn pinmux_poweroff_pinsnpinmux_powerdown_input_pinsnfpga_boot0_pins nfpga_boot1_pins nrtvxpinmux_touchscreen_irq_pinsn4pinmux_touchscreen_wake_pinsn pinmux_dss_dpi_pinsnpinmux_lte430_pinsn8pinmux_backlight_pinsn:scm_conf@270sysconsimple-busp0+ p0 pbias_regulator@2b0ti,pbias-omap3ti,pbias-omap pbias_mmc_omap2430pbias_mmc_omap2430w@-clocks+mcbsp5_mux_fck@68ti,composite-mux-clock hmcbsp5_fckti,composite-clockmcbsp1_mux_fck@4ti,composite-mux-clock mcbsp1_fckti,composite-clockmcbsp2_mux_fck@4ti,composite-mux-clockmcbsp2_fckti,composite-clockmcbsp3_mux_fck@68ti,composite-mux-clockhmcbsp3_fckti,composite-clockmcbsp4_mux_fck@68ti,composite-mux-clockhmcbsp4_fckti,composite-clockclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+9pinmux_twl4030_vpins naes@480c5000 ti,omap3-aesaesH PPABtxrx disabledprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockY osc_sys_ck@d40 ti,mux-clock  @!sys_ck@1270ti,divider-clock!p&sys_clkout1@d70ti,gate-clock! pdpll3_x2_ckfixed-factor-clock"2=dpll3_m2x2_ckfixed-factor-clock#2=%dpll4_x2_ckfixed-factor-clock$2=corex2_fckfixed-factor-clock%2='wkup_l4_ickfixed-factor-clock&2=Vcorex2_d3_fckfixed-factor-clock'2=corex2_d5_fckfixed-factor-clock'2=clockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockHvirt_12m_ck fixed-clockvirt_13m_ck fixed-clock]@virt_19200000_ck fixed-clock$virt_26000000_ck fixed-clockvirt_38_4m_ck fixed-clockIdpll4_ck@d00ti,omap3-dpll-per-clock&& D 0$dpll4_m2_ck@d48ti,divider-clock$? H(dpll4_m2x2_mul_ckfixed-factor-clock(2=)dpll4_m2x2_ck@d00ti,gate-clock) G*omap_96m_alwon_fckfixed-factor-clock*2=1dpll3_ck@d00ti,omap3-dpll-core-clock&& @ 0"dpll3_m3_ck@1140ti,divider-clock"@+dpll3_m3x2_mul_ckfixed-factor-clock+2=,dpll3_m3x2_ck@d00ti,gate-clock,  G-emu_core_alwon_ckfixed-factor-clock-2=jsys_altclk fixed-clock6mcbsp_clks fixed-clockdpll3_m2_ck@d40ti,divider-clock" @#core_ckfixed-factor-clock#2=.dpll1_fck@940ti,divider-clock. @/dpll1_ck@904ti,omap3-dpll-clock&/  $ @ 4dpll1_x2_ckfixed-factor-clock2=0dpll1_x2m2_ck@944ti,divider-clock0 DDcm_96m_fckfixed-factor-clock12=2omap_96m_fck@d40 ti,mux-clock2& @Mdpll4_m3_ck@e40ti,divider-clock$ @3dpll4_m3x2_mul_ckfixed-factor-clock32=4dpll4_m3x2_ck@d00ti,gate-clock4 G5omap_54m_fck@d40 ti,mux-clock56 @@cm_96m_d2_fckfixed-factor-clock22=7omap_48m_fck@d40 ti,mux-clock76 @8omap_12m_fckfixed-factor-clock82=Odpll4_m4_ck@e40ti,divider-clock$ @9dpll4_m4x2_mul_ckti,fixed-factor-clock9]kx:dpll4_m4x2_ck@d00ti,gate-clock: Gxdpll4_m5_ck@f40ti,divider-clock$?@;dpll4_m5x2_mul_ckti,fixed-factor-clock;]kx<dpll4_m5x2_ck@d00ti,gate-clock< Gxrdpll4_m6_ck@1140ti,divider-clock$?@=dpll4_m6x2_mul_ckfixed-factor-clock=2=>dpll4_m6x2_ck@d00ti,gate-clock> G?emu_per_alwon_ckfixed-factor-clock?2=kclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock. pAclkout2_src_mux_ck@d70ti,composite-mux-clock.&2@ pBclkout2_src_ckti,composite-clockABCsys_clkout2@d70ti,divider-clockC@ pmpu_ckfixed-factor-clockD2=Earm_fck@924ti,divider-clockE $emu_mpu_alwon_ckfixed-factor-clockE2=ll3_ick@a40ti,divider-clock. @Fl4_ick@a40ti,divider-clockF @Grm_ick@c40ti,divider-clockG @gpt10_gate_fck@a00ti,composite-gate-clock&  Igpt10_mux_fck@a40ti,composite-mux-clockH& @Jgpt10_fckti,composite-clockIJgpt11_gate_fck@a00ti,composite-gate-clock&  Kgpt11_mux_fck@a40ti,composite-mux-clockH& @Lgpt11_fckti,composite-clockKLcore_96m_fckfixed-factor-clockM2= mmchs2_fck@a00ti,wait-gate-clock  mmchs1_fck@a00ti,wait-gate-clock  i2c3_fck@a00ti,wait-gate-clock  i2c2_fck@a00ti,wait-gate-clock  i2c1_fck@a00ti,wait-gate-clock  mcbsp5_gate_fck@a00ti,composite-gate-clock  mcbsp1_gate_fck@a00ti,composite-gate-clock  core_48m_fckfixed-factor-clock82=Nmcspi4_fck@a00ti,wait-gate-clockN mcspi3_fck@a00ti,wait-gate-clockN mcspi2_fck@a00ti,wait-gate-clockN mcspi1_fck@a00ti,wait-gate-clockN uart2_fck@a00ti,wait-gate-clockN uart1_fck@a00ti,wait-gate-clockN  core_12m_fckfixed-factor-clockO2=Phdq_fck@a00ti,wait-gate-clockP core_l3_ickfixed-factor-clockF2=Qsdrc_ick@a10ti,wait-gate-clockQ gpmc_fckfixed-factor-clockQ2=core_l4_ickfixed-factor-clockG2=Rmmchs2_ick@a10ti,omap3-interface-clockR mmchs1_ick@a10ti,omap3-interface-clockR hdq_ick@a10ti,omap3-interface-clockR mcspi4_ick@a10ti,omap3-interface-clockR mcspi3_ick@a10ti,omap3-interface-clockR mcspi2_ick@a10ti,omap3-interface-clockR mcspi1_ick@a10ti,omap3-interface-clockR i2c3_ick@a10ti,omap3-interface-clockR i2c2_ick@a10ti,omap3-interface-clockR i2c1_ick@a10ti,omap3-interface-clockR uart2_ick@a10ti,omap3-interface-clockR uart1_ick@a10ti,omap3-interface-clockR  gpt11_ick@a10ti,omap3-interface-clockR  gpt10_ick@a10ti,omap3-interface-clockR  mcbsp5_ick@a10ti,omap3-interface-clockR  mcbsp1_ick@a10ti,omap3-interface-clockR  omapctrl_ick@a10ti,omap3-interface-clockR dss_tv_fck@e00ti,gate-clock@dss_96m_fck@e00ti,gate-clockMdss2_alwon_fck@e00ti,gate-clock&dummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock& Sgpt1_mux_fck@c40ti,composite-mux-clockH& @Tgpt1_fckti,composite-clockSTaes2_ick@a10ti,omap3-interface-clockR wkup_32k_fckfixed-factor-clockH2=Ugpio1_dbck@c00ti,gate-clockU sha12_ick@a10ti,omap3-interface-clockR wdt2_fck@c00ti,wait-gate-clockU wdt2_ick@c10ti,omap3-interface-clockV wdt1_ick@c10ti,omap3-interface-clockV gpio1_ick@c10ti,omap3-interface-clockV omap_32ksync_ick@c10ti,omap3-interface-clockV gpt12_ick@c10ti,omap3-interface-clockV gpt1_ick@c10ti,omap3-interface-clockV per_96m_fckfixed-factor-clock12=per_48m_fckfixed-factor-clock82=Wuart3_fck@1000ti,wait-gate-clockW gpt2_gate_fck@1000ti,composite-gate-clock&Xgpt2_mux_fck@1040ti,composite-mux-clockH&@Ygpt2_fckti,composite-clockXYgpt3_gate_fck@1000ti,composite-gate-clock&Zgpt3_mux_fck@1040ti,composite-mux-clockH&@[gpt3_fckti,composite-clockZ[gpt4_gate_fck@1000ti,composite-gate-clock&\gpt4_mux_fck@1040ti,composite-mux-clockH&@]gpt4_fckti,composite-clock\]gpt5_gate_fck@1000ti,composite-gate-clock&^gpt5_mux_fck@1040ti,composite-mux-clockH&@_gpt5_fckti,composite-clock^_gpt6_gate_fck@1000ti,composite-gate-clock&`gpt6_mux_fck@1040ti,composite-mux-clockH&@agpt6_fckti,composite-clock`agpt7_gate_fck@1000ti,composite-gate-clock&bgpt7_mux_fck@1040ti,composite-mux-clockH&@cgpt7_fckti,composite-clockbcgpt8_gate_fck@1000ti,composite-gate-clock& dgpt8_mux_fck@1040ti,composite-mux-clockH&@egpt8_fckti,composite-clockdegpt9_gate_fck@1000ti,composite-gate-clock& fgpt9_mux_fck@1040ti,composite-mux-clockH&@ggpt9_fckti,composite-clockfgper_32k_alwon_fckfixed-factor-clockH2=hgpio6_dbck@1000ti,gate-clockhgpio5_dbck@1000ti,gate-clockhgpio4_dbck@1000ti,gate-clockhgpio3_dbck@1000ti,gate-clockhgpio2_dbck@1000ti,gate-clockh wdt3_fck@1000ti,wait-gate-clockh per_l4_ickfixed-factor-clockG2=igpio6_ick@1010ti,omap3-interface-clockigpio5_ick@1010ti,omap3-interface-clockigpio4_ick@1010ti,omap3-interface-clockigpio3_ick@1010ti,omap3-interface-clockigpio2_ick@1010ti,omap3-interface-clocki wdt3_ick@1010ti,omap3-interface-clocki uart3_ick@1010ti,omap3-interface-clocki uart4_ick@1010ti,omap3-interface-clockigpt9_ick@1010ti,omap3-interface-clocki gpt8_ick@1010ti,omap3-interface-clocki gpt7_ick@1010ti,omap3-interface-clockigpt6_ick@1010ti,omap3-interface-clockigpt5_ick@1010ti,omap3-interface-clockigpt4_ick@1010ti,omap3-interface-clockigpt3_ick@1010ti,omap3-interface-clockigpt2_ick@1010ti,omap3-interface-clockimcbsp2_ick@1010ti,omap3-interface-clockimcbsp3_ick@1010ti,omap3-interface-clockimcbsp4_ick@1010ti,omap3-interface-clockimcbsp2_gate_fck@1000ti,composite-gate-clockmcbsp3_gate_fck@1000ti,composite-gate-clockmcbsp4_gate_fck@1000ti,composite-gate-clockemu_src_mux_ck@1140 ti,mux-clock&jkl@memu_src_ckti,clkdm-gate-clockmnpclk_fck@1140ti,divider-clockn@pclkx2_fck@1140ti,divider-clockn@atclk_fck@1140ti,divider-clockn@traceclk_src_fck@1140 ti,mux-clock&jkl@otraceclk_fck@1140ti,divider-clocko @secure_32k_fck fixed-clockpgpt12_fckfixed-factor-clockp2=wdt1_fckfixed-factor-clockp2=security_l4_ick2fixed-factor-clockG2=qaes1_ick@a14ti,omap3-interface-clockq rng_ick@a14ti,omap3-interface-clockq sha11_ick@a14ti,omap3-interface-clockq des1_ick@a14ti,omap3-interface-clockq cam_mclk@f00ti,gate-clockrxcam_ick@f10!ti,omap3-no-wait-interface-clockGcsi2_96m_fck@f00ti,gate-clock security_l3_ickfixed-factor-clockF2=spka_ick@a14ti,omap3-interface-clocks icr_ick@a10ti,omap3-interface-clockR des2_ick@a10ti,omap3-interface-clockR mspro_ick@a10ti,omap3-interface-clockR mailboxes_ick@a10ti,omap3-interface-clockR ssi_l4_ickfixed-factor-clockG2=zsr1_fck@c00ti,wait-gate-clock&  sr2_fck@c00ti,wait-gate-clock&  sr_l4_ickfixed-factor-clockG2=dpll2_fck@40ti,divider-clock.@tdpll2_ck@4ti,omap3-dpll-clock&t$@4udpll2_m2_ck@44ti,divider-clockuDviva2_ck@0ti,wait-gate-clockvmodem_fck@a00ti,omap3-interface-clock& sad2d_ick@a10ti,omap3-interface-clockF mad2d_ick@a18ti,omap3-interface-clockF mspro_fck@a00ti,wait-gate-clock  ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock' wssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock' @$xssi_ssr_fck_3430es2ti,composite-clockwxyssi_sst_fck_3430es2fixed-factor-clocky2=hsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clockQ ssi_ick_3430es2@a10ti,omap3-ssi-interface-clockz usim_gate_fck@c00ti,composite-gate-clockM  sys_d2_ckfixed-factor-clock&2=|omap_96m_d2_fckfixed-factor-clockM2=}omap_96m_d4_fckfixed-factor-clockM2=~omap_96m_d8_fckfixed-factor-clockM2=omap_96m_d10_fckfixed-factor-clockM2= dpll5_m2_d4_ckfixed-factor-clock{2=dpll5_m2_d8_ckfixed-factor-clock{2=dpll5_m2_d16_ckfixed-factor-clock{2=dpll5_m2_d20_ckfixed-factor-clock{2=usim_mux_fck@c40ti,composite-mux-clock(&|}~ @usim_fckti,composite-clockusim_ick@c10ti,omap3-interface-clockV  dpll5_ck@d04ti,omap3-dpll-clock&&  $ L 4dpll5_m2_ck@d50ti,divider-clock P{sgx_gate_fck@b00ti,composite-gate-clock. core_d3_ckfixed-factor-clock.2=core_d4_ckfixed-factor-clock.2=core_d6_ckfixed-factor-clock.2=omap_192m_alwon_fckfixed-factor-clock*2=core_d2_ckfixed-factor-clock.2=sgx_mux_fck@b40ti,composite-mux-clock 2 @sgx_fckti,composite-clocksgx_ick@b10ti,wait-gate-clockF cpefuse_fck@a08ti,gate-clock& ts_fck@a08ti,gate-clockH usbtll_fck@a08ti,wait-gate-clock{ usbtll_ick@a18ti,omap3-interface-clockR mmchs3_ick@a10ti,omap3-interface-clockR mmchs3_fck@a00ti,wait-gate-clock  dss1_alwon_fck_3430es2@e00ti,dss-gate-clockxdss_ick_3430es2@e10ti,omap3-dss-interface-clockGusbhost_120m_fck@1400ti,gate-clock{usbhost_48m_fck@1400ti,dss-gate-clock8usbhost_ick@1410ti,omap3-dss-interface-clockGclockdomainscore_l3_clkdmti,clockdomaindpll3_clkdmti,clockdomain"dpll1_clkdmti,clockdomainper_clkdmti,clockdomainhemu_clkdmti,clockdomainndpll4_clkdmti,clockdomain$wkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomainud2d_clkdmti,clockdomain dpll5_clkdmti,clockdomainsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain counter@48320000ti,omap-counter32kH2  counter_32kinterrupt-controller@48200000ti,omap3-intcH dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaH`  `dmagpio@48310000ti,omap3-gpioH1gpio1"gpio@49050000ti,omap3-gpioIgpio2"gpio@49052000ti,omap3-gpioI gpio3"gpio@49054000ti,omap3-gpioI@ gpio4"gpio@49056000ti,omap3-gpioI`!gpio5"gpio@49058000ti,omap3-gpioI"gpio6" serial@4806a000ti,omap3-uartH .H12txrxuart1lserial@4806c000ti,omap3-uartH.I34txrxuart2lserial@49020000ti,omap3-uartI.J56txrxuart3lVdefaultdi2c@48070000 ti,omap3-i2cH8txrx+i2c1'@twl@48H  ti,twl4030Vdefaultdaudioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci BP \vacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2 vdd_ehciw@w@mregulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0regulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5regulator-vusb1v8ti,twl4030-vusb1v8regulator-vusb3v1ti,twl4030-vusb3v1regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@mregulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpio"twl4030-usbti,twl4030-usb pwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadmadcti,twl4030-madci2c@48072000 ti,omap3-i2cH 9txrx+i2c2 disabledi2c@48060000 ti,omap3-i2cH=txrx+i2c3Vdefaultdmailbox@48094000ti,omap3-mailboxmailboxH @#/Adsp S ^spi@48098000ti,omap2-mcspiH A+mcspi1i@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3Vdefaultdspidev@0spidevwlspi@4809a000ti,omap2-mcspiH B+mcspi2i +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [+mcspi3i tx0rx0tx1rx1Vdefaultdspidev@0spidevwlspi@480ba000ti,omap2-mcspiH 0+mcspi4iFGtx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1=>txrxVdefaultd mmc@480b4000ti,omap3-hsmmcH @Vmmc2/0txrxVdefaultdmmc@480ad000ti,omap3-hsmmcH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuH mmu_isp mmu@5d000000ti,omap2-iommu]mmu_iva disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@mpu ;<  commontxrx0mcbsp1 txrxfck disabledmcbsp@49022000ti,omap3-mcbspI I mpusidetone>? commontxrxsidetone0mcbsp2mcbsp2_sidetone!"txrxfckickokaymcbsp@49024000ti,omap3-mcbspI@I mpusidetoneYZ commontxrxsidetone0mcbsp3mcbsp3_sidetonetxrxfckickokayVdefaultdmcbsp@49026000ti,omap3-mcbspI`mpu 67  commontxrx0mcbsp4txrxfck? disabledmcbsp@48096000ti,omap3-mcbspH `mpu QR  commontxrx0mcbsp5txrxfck disabledsham@480c3000ti,omap3-shamshamH 0d1Erx disabledtimer@48318000ti,omap3430-timerH1%timer1Ptimer@49032000ti,omap3430-timerI &timer2timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5_timer@4903a000ti,omap3430-timerI*timer6_timer@4903c000ti,omap3430-timerI+timer7_timer@4903e000ti,omap3430-timerI,timer8l_timer@49040000ti,omap3430-timerI-timer9ltimer@48086000ti,omap3430-timerH`.timer10ltimer@48088000ti,omap3430-timerH/timer11ltimer@48304000ti,omap3430-timerH0@_timer12Pyusbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs+ ehci-phyohci@48064400ti,ohci-omap3HDLehci@48064800 ti,ehci-omapHHMgpmc@6e000000ti,omap3430-gpmcgpmcnrxtx+"0nand@0,0ti,omap2-nand  sw$ $2AT$gu0HH6+x-loader@0 X-Loaderbootloaders@80000U-Bootbootloaders_env@260000 U-Boot Env&kernel@280000Kernel(@filesystem@680000 File Systemhusb_otg_hs@480ab000ti,omap3-musbH \] mcdma usb_otg_hs  usb2-phy'2dss@48050000 ti,omap3-dssHok dss_corefck+Vdefaultddispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H protophypll disabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbiH disabled dss_rfbifckickencoder@48050c00ti,omap3-vencH  disabled dss_vencfckportendpoint-=ssi-controller@48058000 ti,omap3-ssissiokHHsysgddG gdd_mpu+ y ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHHtxrxCDssi-port@4805b000ti,omap3-ssi-portHHtxrxEFpinmux@480025d8 ti,omap3-padconfpinctrl-singleH%$+9isp@480bc000 ti,omap3-ispH H |H  lOports+bandgap@48002524H%$ti,omap34xx-bandgap[ target-module@480cb000ti,sysc-omap3430-srti,syscsmartreflex_coreH $syscq fck+ H smartreflex@0ti,omap3-smartreflex-coretarget-module@480c9000ti,sysc-omap3430-srti,syscsmartreflex_mpu_ivaH $syscq fck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivathermal-zonescpu_thermal~N  memory@80000000|memoryhsusb2_power_regregulator-fixed hsusb2_vbus2Z2Z phsusb2_phyusb-nop-xceiv  soundti,omap-twl4030 omap3beagleregulator-mmc2-sdio-poweronregulator-fixedregulator-mmc2-sdio-poweron00 'gpio_poweroffVdefaultdgpio-poweroff  display panel-dpilcdVdefaultd  portendpoint-panel-timingP  ((V4>J Wan{backlightgpio-backlightVdefaultd   compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesstatusclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesregulator-always-onti,use-ledsti,pullupsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyspi-cphati,dual-voltpbias-supplyvmmc-supplyvqmmc-supplycd-gpiosbus-widthnon-removablecap-power-off-card#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-size#sound-dai-cellsti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,wr-access-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsti,sysc-maskpolling-delay-passivepolling-delaycoefficientsthermal-sensorsgpiostartup-delay-usreset-gpiosvcc-supplyti,modelti,mcbspenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activedefault-on