8D( ti,omap3430-sdpti,omap3 +7TI OMAP3430 SDPchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000cpus+cpu@0arm,cortex-a8scpucpu(HАg8 Odp` 'ppmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+$pinmux_twl4030_pinsAAUscm_conf@270sysconsimple-busp0+ p0Upbias_regulator@2b0ti,pbias-omap3ti,pbias-omap]pbias_mmc_omap2430dpbias_mmc_omap2430sw@-Uclocks+mcbsp5_mux_fck@68ti,composite-mux-clockhUmcbsp5_fckti,composite-clockUmcbsp1_mux_fck@4ti,composite-mux-clockU mcbsp1_fckti,composite-clock Umcbsp2_mux_fck@4ti,composite-mux-clock U mcbsp2_fckti,composite-clock Umcbsp3_mux_fck@68ti,composite-mux-clock hUmcbsp3_fckti,composite-clock Umcbsp4_mux_fck@68ti,composite-mux-clock hUmcbsp4_fckti,composite-clockUclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+$pinmux_twl4030_vpins AUaes@480c5000 ti,omap3-aesaesH PPABtxrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockYUosc_sys_ck@d40 ti,mux-clock @Usys_ck@1270ti,divider-clockpUsys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clock dpll3_m2x2_ckfixed-factor-clock Udpll4_x2_ckfixed-factor-clock corex2_fckfixed-factor-clock Uwkup_l4_ickfixed-factor-clock UMcorex2_d3_fckfixed-factor-clock Ucorex2_d5_fckfixed-factor-clock Uclockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockU?virt_12m_ck fixed-clockUvirt_13m_ck fixed-clock]@Uvirt_19200000_ck fixed-clock$Uvirt_26000000_ck fixed-clockUvirt_38_4m_ck fixed-clockIUdpll4_ck@d00ti,omap3-dpll-per-clock D 0Udpll4_m2_ck@d48ti,divider-clock? HUdpll4_m2x2_mul_ckfixed-factor-clock U dpll4_m2x2_ck@d00ti,gate-clock  U!omap_96m_alwon_fckfixed-factor-clock! U(dpll3_ck@d00ti,omap3-dpll-core-clock @ 0Udpll3_m3_ck@1140ti,divider-clock@U"dpll3_m3x2_mul_ckfixed-factor-clock" U#dpll3_m3x2_ck@d00ti,gate-clock#  U$emu_core_alwon_ckfixed-factor-clock$ Uasys_altclk fixed-clockU-mcbsp_clks fixed-clockUdpll3_m2_ck@d40ti,divider-clock @Ucore_ckfixed-factor-clock U%dpll1_fck@940ti,divider-clock% @U&dpll1_ck@904ti,omap3-dpll-clock&  $ @ 4Udpll1_x2_ckfixed-factor-clock U'dpll1_x2m2_ck@944ti,divider-clock' DU;cm_96m_fckfixed-factor-clock( U)omap_96m_fck@d40 ti,mux-clock) @UDdpll4_m3_ck@e40ti,divider-clock @U*dpll4_m3x2_mul_ckfixed-factor-clock* U+dpll4_m3x2_ck@d00ti,gate-clock+ U,omap_54m_fck@d40 ti,mux-clock,- @U7cm_96m_d2_fckfixed-factor-clock) U.omap_48m_fck@d40 ti,mux-clock.- @U/omap_12m_fckfixed-factor-clock/ UFdpll4_m4_ck@e40ti,divider-clock @U0dpll4_m4x2_mul_ckti,fixed-factor-clock0)7DU1dpll4_m4x2_ck@d00ti,gate-clock1 DUdpll4_m5_ck@f40ti,divider-clock?@U2dpll4_m5x2_mul_ckti,fixed-factor-clock2)7DU3dpll4_m5x2_ck@d00ti,gate-clock3 DUidpll4_m6_ck@1140ti,divider-clock?@U4dpll4_m6x2_mul_ckfixed-factor-clock4 U5dpll4_m6x2_ck@d00ti,gate-clock5 U6emu_per_alwon_ckfixed-factor-clock6 Ubclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock% pU8clkout2_src_mux_ck@d70ti,composite-mux-clock%)7 pU9clkout2_src_ckti,composite-clock89U:sys_clkout2@d70ti,divider-clock:@ pWmpu_ckfixed-factor-clock; U<arm_fck@924ti,divider-clock< $emu_mpu_alwon_ckfixed-factor-clock< Ucl3_ick@a40ti,divider-clock% @U=l4_ick@a40ti,divider-clock= @U>rm_ick@c40ti,divider-clock> @gpt10_gate_fck@a00ti,composite-gate-clock  U@gpt10_mux_fck@a40ti,composite-mux-clock? @UAgpt10_fckti,composite-clock@Agpt11_gate_fck@a00ti,composite-gate-clock  UBgpt11_mux_fck@a40ti,composite-mux-clock? @UCgpt11_fckti,composite-clockBCcore_96m_fckfixed-factor-clockD Ummchs2_fck@a00ti,wait-gate-clock Ummchs1_fck@a00ti,wait-gate-clock Ui2c3_fck@a00ti,wait-gate-clock Ui2c2_fck@a00ti,wait-gate-clock Ui2c1_fck@a00ti,wait-gate-clock Umcbsp5_gate_fck@a00ti,composite-gate-clock  Umcbsp1_gate_fck@a00ti,composite-gate-clock  Ucore_48m_fckfixed-factor-clock/ UEmcspi4_fck@a00ti,wait-gate-clockE Umcspi3_fck@a00ti,wait-gate-clockE Umcspi2_fck@a00ti,wait-gate-clockE Umcspi1_fck@a00ti,wait-gate-clockE Uuart2_fck@a00ti,wait-gate-clockE Uuart1_fck@a00ti,wait-gate-clockE  Ucore_12m_fckfixed-factor-clockF UGhdq_fck@a00ti,wait-gate-clockG Ucore_l3_ickfixed-factor-clock= UHsdrc_ick@a10ti,wait-gate-clockH Ugpmc_fckfixed-factor-clockH core_l4_ickfixed-factor-clock> UImmchs2_ick@a10ti,omap3-interface-clockI Ummchs1_ick@a10ti,omap3-interface-clockI Uhdq_ick@a10ti,omap3-interface-clockI Umcspi4_ick@a10ti,omap3-interface-clockI Umcspi3_ick@a10ti,omap3-interface-clockI Umcspi2_ick@a10ti,omap3-interface-clockI Umcspi1_ick@a10ti,omap3-interface-clockI Ui2c3_ick@a10ti,omap3-interface-clockI Ui2c2_ick@a10ti,omap3-interface-clockI Ui2c1_ick@a10ti,omap3-interface-clockI Uuart2_ick@a10ti,omap3-interface-clockI Uuart1_ick@a10ti,omap3-interface-clockI  Ugpt11_ick@a10ti,omap3-interface-clockI  Ugpt10_ick@a10ti,omap3-interface-clockI  Umcbsp5_ick@a10ti,omap3-interface-clockI  Umcbsp1_ick@a10ti,omap3-interface-clockI  Uomapctrl_ick@a10ti,omap3-interface-clockI Udss_tv_fck@e00ti,gate-clock7Udss_96m_fck@e00ti,gate-clockDUdss2_alwon_fck@e00ti,gate-clockUdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock UJgpt1_mux_fck@c40ti,composite-mux-clock? @UKgpt1_fckti,composite-clockJKaes2_ick@a10ti,omap3-interface-clockI Uwkup_32k_fckfixed-factor-clock? ULgpio1_dbck@c00ti,gate-clockL Usha12_ick@a10ti,omap3-interface-clockI Uwdt2_fck@c00ti,wait-gate-clockL Uwdt2_ick@c10ti,omap3-interface-clockM Uwdt1_ick@c10ti,omap3-interface-clockM Ugpio1_ick@c10ti,omap3-interface-clockM Uomap_32ksync_ick@c10ti,omap3-interface-clockM Ugpt12_ick@c10ti,omap3-interface-clockM Ugpt1_ick@c10ti,omap3-interface-clockM Uper_96m_fckfixed-factor-clock( U per_48m_fckfixed-factor-clock/ UNuart3_fck@1000ti,wait-gate-clockN Ugpt2_gate_fck@1000ti,composite-gate-clockUOgpt2_mux_fck@1040ti,composite-mux-clock?@UPgpt2_fckti,composite-clockOPgpt3_gate_fck@1000ti,composite-gate-clockUQgpt3_mux_fck@1040ti,composite-mux-clock?@URgpt3_fckti,composite-clockQRgpt4_gate_fck@1000ti,composite-gate-clockUSgpt4_mux_fck@1040ti,composite-mux-clock?@UTgpt4_fckti,composite-clockSTgpt5_gate_fck@1000ti,composite-gate-clockUUgpt5_mux_fck@1040ti,composite-mux-clock?@UVgpt5_fckti,composite-clockUVgpt6_gate_fck@1000ti,composite-gate-clockUWgpt6_mux_fck@1040ti,composite-mux-clock?@UXgpt6_fckti,composite-clockWXgpt7_gate_fck@1000ti,composite-gate-clockUYgpt7_mux_fck@1040ti,composite-mux-clock?@UZgpt7_fckti,composite-clockYZgpt8_gate_fck@1000ti,composite-gate-clock U[gpt8_mux_fck@1040ti,composite-mux-clock?@U\gpt8_fckti,composite-clock[\gpt9_gate_fck@1000ti,composite-gate-clock U]gpt9_mux_fck@1040ti,composite-mux-clock?@U^gpt9_fckti,composite-clock]^per_32k_alwon_fckfixed-factor-clock? U_gpio6_dbck@1000ti,gate-clock_Ugpio5_dbck@1000ti,gate-clock_Ugpio4_dbck@1000ti,gate-clock_Ugpio3_dbck@1000ti,gate-clock_Ugpio2_dbck@1000ti,gate-clock_ Uwdt3_fck@1000ti,wait-gate-clock_ Uper_l4_ickfixed-factor-clock> U`gpio6_ick@1010ti,omap3-interface-clock`Ugpio5_ick@1010ti,omap3-interface-clock`Ugpio4_ick@1010ti,omap3-interface-clock`Ugpio3_ick@1010ti,omap3-interface-clock`Ugpio2_ick@1010ti,omap3-interface-clock` Uwdt3_ick@1010ti,omap3-interface-clock` Uuart3_ick@1010ti,omap3-interface-clock` Uuart4_ick@1010ti,omap3-interface-clock`Ugpt9_ick@1010ti,omap3-interface-clock` Ugpt8_ick@1010ti,omap3-interface-clock` Ugpt7_ick@1010ti,omap3-interface-clock`Ugpt6_ick@1010ti,omap3-interface-clock`Ugpt5_ick@1010ti,omap3-interface-clock`Ugpt4_ick@1010ti,omap3-interface-clock`Ugpt3_ick@1010ti,omap3-interface-clock`Ugpt2_ick@1010ti,omap3-interface-clock`Umcbsp2_ick@1010ti,omap3-interface-clock`Umcbsp3_ick@1010ti,omap3-interface-clock`Umcbsp4_ick@1010ti,omap3-interface-clock`Umcbsp2_gate_fck@1000ti,composite-gate-clockU mcbsp3_gate_fck@1000ti,composite-gate-clockU mcbsp4_gate_fck@1000ti,composite-gate-clockUemu_src_mux_ck@1140 ti,mux-clockabc@Udemu_src_ckti,clkdm-gate-clockdUepclk_fck@1140ti,divider-clocke@pclkx2_fck@1140ti,divider-clocke@atclk_fck@1140ti,divider-clocke@traceclk_src_fck@1140 ti,mux-clockabc@Uftraceclk_fck@1140ti,divider-clockf @secure_32k_fck fixed-clockUggpt12_fckfixed-factor-clockg wdt1_fckfixed-factor-clockg security_l4_ick2fixed-factor-clock> Uhaes1_ick@a14ti,omap3-interface-clockh rng_ick@a14ti,omap3-interface-clockh sha11_ick@a14ti,omap3-interface-clockh des1_ick@a14ti,omap3-interface-clockh cam_mclk@f00ti,gate-clockiDcam_ick@f10!ti,omap3-no-wait-interface-clock>Ucsi2_96m_fck@f00ti,gate-clockUsecurity_l3_ickfixed-factor-clock= Ujpka_ick@a14ti,omap3-interface-clockj icr_ick@a10ti,omap3-interface-clockI des2_ick@a10ti,omap3-interface-clockI mspro_ick@a10ti,omap3-interface-clockI mailboxes_ick@a10ti,omap3-interface-clockI ssi_l4_ickfixed-factor-clock> Uqsr1_fck@c00ti,wait-gate-clock Usr2_fck@c00ti,wait-gate-clock Usr_l4_ickfixed-factor-clock> dpll2_fck@40ti,divider-clock%@Ukdpll2_ck@4ti,omap3-dpll-clockk$@4mUldpll2_m2_ck@44ti,divider-clocklDUmiva2_ck@0ti,wait-gate-clockmUmodem_fck@a00ti,omap3-interface-clock Usad2d_ick@a10ti,omap3-interface-clock= Umad2d_ick@a18ti,omap3-interface-clock= Umspro_fck@a00ti,wait-gate-clock ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock Unssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock @$Uossi_ssr_fck_3430es2ti,composite-clocknoUpssi_sst_fck_3430es2fixed-factor-clockp Uhsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clockH Ussi_ick_3430es2@a10ti,omap3-ssi-interface-clockq Uusim_gate_fck@c00ti,composite-gate-clockD  U|sys_d2_ckfixed-factor-clock Usomap_96m_d2_fckfixed-factor-clockD Utomap_96m_d4_fckfixed-factor-clockD Uuomap_96m_d8_fckfixed-factor-clockD Uvomap_96m_d10_fckfixed-factor-clockD Uwdpll5_m2_d4_ckfixed-factor-clockr Uxdpll5_m2_d8_ckfixed-factor-clockr Uydpll5_m2_d16_ckfixed-factor-clockr Uzdpll5_m2_d20_ckfixed-factor-clockr U{usim_mux_fck@c40ti,composite-mux-clock(stuvwxyz{ @U}usim_fckti,composite-clock|}usim_ick@c10ti,omap3-interface-clockM  Udpll5_ck@d04ti,omap3-dpll-clock  $ L 4mU~dpll5_m2_ck@d50ti,divider-clock~ PUrsgx_gate_fck@b00ti,composite-gate-clock% Ucore_d3_ckfixed-factor-clock% Ucore_d4_ckfixed-factor-clock% Ucore_d6_ckfixed-factor-clock% Uomap_192m_alwon_fckfixed-factor-clock! Ucore_d2_ckfixed-factor-clock% Usgx_mux_fck@b40ti,composite-mux-clock ) @Usgx_fckti,composite-clocksgx_ick@b10ti,wait-gate-clock= Ucpefuse_fck@a08ti,gate-clock Uts_fck@a08ti,gate-clock? Uusbtll_fck@a08ti,wait-gate-clockr Uusbtll_ick@a18ti,omap3-interface-clockI Ummchs3_ick@a10ti,omap3-interface-clockI Ummchs3_fck@a00ti,wait-gate-clock Udss1_alwon_fck_3430es2@e00ti,dss-gate-clockDUdss_ick_3430es2@e10ti,omap3-dss-interface-clock>Uusbhost_120m_fck@1400ti,gate-clockrUusbhost_48m_fck@1400ti,dss-gate-clock/Uusbhost_ick@1410ti,omap3-dss-interface-clock>Uclockdomainscore_l3_clkdmti,clockdomaindpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainhemu_clkdmti,clockdomainedpll4_clkdmti,clockdomainwkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomainld2d_clkdmti,clockdomain dpll5_clkdmti,clockdomain~sgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain counter@48320000ti,omap-counter32kH2  counter_32kinterrupt-controller@48200000ti,omap3-intcH Udma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaH`  `dmaUgpio@48310000ti,omap3-gpioH1gpio1gpio@49050000ti,omap3-gpioIgpio2gpio@49052000ti,omap3-gpioI gpio3gpio@49054000ti,omap3-gpioI@ gpio4gpio@49056000ti,omap3-gpioI`!gpio5gpio@49058000ti,omap3-gpioI"gpio6serial@4806a000ti,omap3-uartH H12txrxuart1lserial@4806c000ti,omap3-uartHI34txrxuart2lserial@49020000ti,omap3-uartIJ56txrxuart3li2c@48070000 ti,omap3-i2cH8txrx+i2c1'@twl@48H ti,twl4030defaultrtcti,twl4030-rtc bciti,twl4030-bci &4 @vacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1s ' regulator-vdacti,twl4030-vdacsw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1s:0Uregulator-vmmc2ti,twl4030-vmmc2s:0regulator-vusb1v5ti,twl4030-vusb1v5Uregulator-vusb1v8ti,twl4030-vusb1v8Uregulator-vusb3v1ti,twl4030-vusb3v1Uregulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2sw@w@regulator-vsimti,twl4030-vsimsw@-Ugpioti,twl4030-gpiotwl4030-usbti,twl4030-usb Q_m{pwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadmadcti,twl4030-madcUi2c@48072000 ti,omap3-i2cH 9txrx+i2c2i2c@48060000 ti,omap3-i2cH=txrx+i2c3mailbox@48094000ti,omap3-mailboxmailboxH @dsp   spi@48098000ti,omap2-mcspiH A+mcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspiH B+mcspi2 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [+mcspi3 tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0+mcspi4FGtx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1#=>txrx0=IVmmc@480b4000ti,omap3-hsmmcH @Vmmc2/0txrx `disabledmmc@480ad000ti,omap3-hsmmcH ^mmc3MNtxrx `disabledmmu@480bd400gti,omap2-iommuH mmu_isptUmmu@5d000000gti,omap2-iommu]mmu_iva `disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@mpu ;< commontxrxmcbsp1 txrxfck `disabledmcbsp@49022000ti,omap3-mcbspI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrxfckick `disabledmcbsp@49024000ti,omap3-mcbspI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrxfckick `disabledmcbsp@49026000ti,omap3-mcbspI`mpu 67 commontxrxmcbsp4txrxfck `disabledmcbsp@48096000ti,omap3-mcbspH `mpu QR commontxrxmcbsp5txrxfck `disabledsham@480c3000ti,omap3-shamshamH 0d1Erxtimer@48318000ti,omap3430-timerH1%timer1timer@49032000ti,omap3430-timerI &timer2timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8timer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11timer@48304000ti,omap3430-timerH0@_timer12usbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs+ohci@48064400ti,ohci-omap3HDLehci@48064800 ti,ehci-omapHHMgpmc@6e000000ti,omap3430-gpmcgpmcnrxtx+0( Unor@0,0 cfi-flash-intel,pf48f6000m0y1be+ <GYgy 0066 r+E \vZpartition@0bootloader-norpartition@40000 params-norpartition@80000 kernel-nor partition@280000filesystem-nor$nand@1,0ti,omap2-nand  -micron,mt29f1g08abb+swYg$y$$0H H6partition@0 xloader-nandpartition@80000bootloader-nandpartition@1c0000 params-nand partition@280000 kernel-nand(Ppartition@780000filesystem-nandxonenand@2,0-samsung,kfm2g16q2m-deb8+ti,omap2-onenand GYgTyHT*l `Nvpartition@0xloader-onenandpartition@80000bootloader-onenandpartition@c0000params-onenand partition@e0000kernel-onenand partition@2e0000filesystem-onenand.usb_otg_hs@480ab000ti,omap3-musbH \]mcdma usb_otg_hs  dss@48050000 ti,omap3-dssH `disabled dss_corefck+dispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H protophypll `disabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbiH `disabled dss_rfbifckickencoder@48050c00ti,omap3-vencH  `disabled dss_vencfckssi-controller@48058000 ti,omap3-ssissi`okHHsysgddGgdd_mpu+ p ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHHtxrxCDssi-port@4805b000ti,omap3-ssi-portHHtxrxEFpinmux@480025d8 ti,omap3-padconfpinctrl-singleH%$+$isp@480bc000 ti,omap3-ispH H |']l.ports+bandgap@48002524H%$ti,omap34xx-bandgap:Utarget-module@480cb000ti,sysc-omap3430-srti,syscsmartreflex_coreH $syscPfck+ H smartreflex@0ti,omap3-smartreflex-coretarget-module@480c9000ti,sysc-omap3430-srti,syscsmartreflex_mpu_ivaH $syscPfck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivathermal-zonescpu_thermal]sN memory@80000000smemory compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyio-channelsio-channel-namesusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplyvqmmc-supplybus-widthstatus#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-size#sound-dai-cellsti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureremote-wakeup-connectedgpmc,num-csgpmc,num-waitpinslinux,mtd-namebank-widthgpmc,mux-add-datagpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenlabelti,nand-ecc-optnand-bus-widthgpmc,device-widthmultipointnum-epsram-bitsiommusti,phy-type#thermal-sensor-cellsti,sysc-maskpolling-delay-passivepolling-delaycoefficientsthermal-sensors