o8d( ,compulab,omap5-cm-t54ti,omap5&7CompuLab CM-T54chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/i2c@4807a000Q/ocp/i2c@4807c000V/ocp/mmc@4809c000[/ocp/mmc@480b4000`/ocp/mmc@480ad000e/ocp/mmc@480d1000j/ocp/mmc@480d5000o/ocp/serial@4806a000w/ocp/serial@4806c000/ocp/serial@48020000/ocp/serial@4806e000/ocp/serial@48066000/ocp/serial@48068000 /connector0 /connector1 /displaycpuscpu@0cpuarm,cortex-a15B@,`cpu cpu@1cpuarm,cortex-a15B@,`cputhermal-zonescpu_thermal5CSAtripscpu_alert`lpassivecpu_crit`Hl criticalcooling-mapsmap0w |gpu_thermal5CSuPtripsgpu_crit`Hl criticalcore_thermal5CStripscore_crit`Hl criticaltimerarm,armv7-timer0   &pmuarm,cortex-a15-pmuinterrupt-controller@48211000arm,cortex-a15-gic@H!H! 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$,(dpll_core_x2_ckti,omap4-dpll-x2-clockdpll_core_h21x2_ck@150ti,divider-clock?Pc2c_fclkfixed-factor-clockc2c_iclkfixed-factor-clockdpll_core_h11x2_ck@138ti,divider-clock?8dpll_core_h12x2_ck@13cti,divider-clock?<dpll_core_h13x2_ck@140ti,divider-clock?@dpll_core_h14x2_ck@144ti,divider-clock?D<dpll_core_h22x2_ck@154ti,divider-clock?Tdpll_core_h23x2_ck@158ti,divider-clock?Xdpll_core_h24x2_ck@15cti,divider-clock?\dpll_core_m2_ck@130ti,divider-clock0dpll_core_m3x2_ck@134ti,divider-clock4Giva_dpll_hs_clk_divfixed-factor-clockdpll_iva_byp_mux@1ac ti,mux-clockdpll_iva_ck@1a0ti,omap4-dpll-clock,Ep}@dpll_iva_x2_ckti,omap4-dpll-x2-clockdpll_iva_h11x2_ck@1b8ti,divider-clock? ,` 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ti,mux-clock+L,dpll_per_ck@140ti,omap4-dpll-clock,@DLH-dpll_per_x2_ckti,omap4-dpll-x2-clock-.dpll_per_h11x2_ck@158ti,divider-clock.?X4dpll_per_h12x2_ck@15cti,divider-clock.?\dpll_per_h14x2_ck@164ti,divider-clock.?d=dpll_per_m2_ck@150ti,divider-clock-P6dpll_per_m2x2_ck@150ti,divider-clock.P5dpll_per_m3x2_ck@154ti,divider-clock.THdpll_unipro1_ck@200ti,omap4-dpll-clock /dpll_unipro1_clkdcoldofixed-factor-clock/9dpll_unipro1_m2_ck@210ti,divider-clock/:dpll_unipro2_ck@1c0ti,omap4-dpll-clock0dpll_unipro2_clkdcoldofixed-factor-clock0dpll_unipro2_m2_ck@1d0ti,divider-clock0dpll_usb_byp_mux@18c ti,mux-clock12dpll_usb_ck@180ti,omap4-dpll-j-type-clock23dpll_usb_clkdcoldofixed-factor-clock3dpll_usb_m2_ck@190ti,divider-clock37func_128m_clkfixed-factor-clock4func_12m_fclkfixed-factor-clock5func_24m_clkfixed-factor-clock6(func_48m_fclkfixed-factor-clock5func_96m_fclkfixed-factor-clock58l3init_60m_fclk@104ti,divider-clock7viss_ctrlclk@1320ti,gate-clock8 lli_txphy_clk@f20ti,gate-clock9 lli_txphy_ls_clk@f20ti,gate-clock:  usb_phy_cm_clk32k@640ti,gate-clock;@tfdif_fclk@1328ti,divider-clock4(gpu_core_gclk_mux@1520 ti,mux-clock<= gpu_hyd_gclk_mux@1520 ti,mux-clock<= hsi_fclk@1638ti,divider-clock58clockdomainsl3init_clkdmti,clockdomain3l3main1_cm@700 ti,omap4-cm clk@20 ti,clkctrl l3main2_cm@800 ti,omap4-cm clk@20 ti,clkctrl ipu_cm@900 ti,omap4-cm   clk@20 ti,clkctrl dma_cm@a00 ti,omap4-cm   clk@20 ti,clkctrl emif_cm@b00 ti,omap4-cm   clk@20 ti,clkctrl l4cfg_cm@d00 ti,omap4-cm   clk@20 ti,clkctrl l3instr_cm@e00 ti,omap4-cm clk@20 ti,clkctrl l4per_cm@1000 ti,omap4-cm clk@20 ti,clkctrl \dss_cm@1400 ti,omap4-cm clk@20 ti,clkctrl |l3init_cm@1600 ti,omap4-cm clk@20 ti,clkctrl ul4@4ae00000ti,omap5-l4-wkupsimple-bus Jcounter@4000ti,omap-counter32k@@ counter_32kprm@6000ti,omap5-prmsimple-bus`0   `0clockssys_clkin@110 ti,mux-clock>?@ABCDabe_dpll_bypass_clk_mux@108 ti,mux-clock;abe_dpll_clk_mux@10c ti,mux-clock; custefuse_sys_gfclk_divfixed-factor-clockdss_syc_gfclk_divfixed-factor-clock'wkupaon_iclk_mux@108 ti,mux-clockEFl3instr_ts_gclk_divfixed-factor-clockFclockdomainswkupaon_cm@1900 ti,omap4-cm clk@20 ti,clkctrl \nscrm@a000ti,omap5-scrm clocksauxclk0_src_gate_ck@310 ti,composite-no-wait-gate-clockGIauxclk0_src_mux_ck@310ti,composite-mux-clock GHJauxclk0_src_ckti,composite-clockIJKauxclk0_ck@310ti,divider-clockKXauxclk1_src_gate_ck@314 ti,composite-no-wait-gate-clockGLauxclk1_src_mux_ck@314ti,composite-mux-clock GHMauxclk1_src_ckti,composite-clockLMNauxclk1_ck@314ti,divider-clockNYauxclk2_src_gate_ck@318 ti,composite-no-wait-gate-clockGOauxclk2_src_mux_ck@318ti,composite-mux-clock GHPauxclk2_src_ckti,composite-clockOPQauxclk2_ck@318ti,divider-clockQZauxclk3_src_gate_ck@31c ti,composite-no-wait-gate-clockGRauxclk3_src_mux_ck@31cti,composite-mux-clock GHSauxclk3_src_ckti,composite-clockRSTauxclk3_ck@31cti,divider-clockT[auxclk4_src_gate_ck@320 ti,composite-no-wait-gate-clockG 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