Ð þíPÕ8K°(%Kx',mundoreader,bq-curie2rockchip,rk3066a 7bq Curie 2aliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/dwmmc@1021c000f/dwmmc@10214000l/dwmmc@10218000r/serial@10124000z/serial@10126000‚/serial@20064000Š/serial@20068000’/spi@20070000—/spi@20074000amba ,simple-busœdma-controller@20018000,arm,pl330arm,primecell£ €@§²½ØÀ ßapb_pclkëdma-controller@2001c000,arm,pl330arm,primecell£ À@§²½ØÀ ßapb_pclk ódisableddma-controller@20078000,arm,pl330arm,primecell£ €@§²½ØÁ ßapb_pclkë oscillator ,fixed-clockún6 xin24mgpu@10090000",rockchip,rk3066-maliarm,mali-400£ ØÅÅ ßbuscore*Å:õáOx ódisabledx§5Vgpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3l2-cache-controller@10138000,arm,pl310-cache£€ftë'scu@1013c000,arm,cortex-a9-scu£Àglobal-timer@1013c200,arm,cortex-a9-global-timer£  § Ølocal-timer@1013c600,arm,cortex-a9-twd-timer£Æ  § Øinterrupt-controller@1013d000,arm,cortex-a9-gic€•£ÐÁëserial@10124000&,rockchip,rk3066-uartsnps,dw-apb-uart£@ §"¦°ßbaudclkapb_pclkØ@Lóokay½ÂtxrxÌdefaultÚserial@10126000&,rockchip,rk3066-uartsnps,dw-apb-uart£` §#¦°ßbaudclkapb_pclkØAMóokay½ÂtxrxÌdefaultÚusb@10180000,rockchip,rk3066-usbsnps,dwc2£ §ØÃßotgäotgìþ €€@@  !usb2-phy ódisabledusb@101c0000 ,snps,dwc2£ §ØÉßotgähost !usb2-phy ódisabledethernet@10204000,rockchip,rk3066-emac£ @< §+ØÄD ßhclkmacref8dBrmii ódisableddwmmc@10214000,rockchip,rk2928-dw-mshc£!@ §ØÀHßbiuciu½ Ârx-txKOQVresetóokayúúð€búð€ÌdefaultÚ p|†˜©dwmmc@10218000,rockchip,rk2928-dw-mshc£!€ §ØÁIßbiuciu½ Ârx-txKORVresetóokayÌdefault Ú´|©dwmmc@1021c000,rockchip,rk2928-dw-mshc£!À §ØÂJßbiuciu½ Ârx-txKOSVreset ódisabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd£ @reboot-mode,syscon-reboot-modeÂ@ÉRBÃÕRBÃãRBà óRBÃgrf@20008000,syscon£ €ëi2c@2002d000,rockchip,rk3066-i2c£ Ð §(+ßi2cØP ódisabledÌdefaultÚi2c@2002f000,rockchip,rk3066-i2c£ ð §)+ØQßi2cóokayÌdefaultÚú€tps@2d£-§ÿ  ,ti,tps65910regulatorsregulator@0vcc_rtc&£:vrtcregulator@1vcc_io&£:vioëregulator@2vdd_armO 'Àgã`&£:vdd1ë(regulator@3vcc_ddrO 'Àgã`&£:vdd2regulator@5 vcc18_cif&£:vdig1regulator@6vdd_11&£:vdig2regulator@7vcc_25&£:vpllregulator@8vcc_18&£:vdacregulator@9 vcc25_hdmi&£ :vaux1regulator@10vcca_33&£ :vaux2regulator@11vcc_tp&£ :vaux33regulator@12 vcc28_cif&£ :vmmcregulator@4£:vdd3regulator@13£ :vbbpwm@20030000,rockchip,rk2928-pwm£ ‘ØF ódisabledÌdefaultÚpwm@20030010,rockchip,rk2928-pwm£ ‘ØF ódisabledÌdefaultÚwatchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt£ ÀØK §3óokaypwm@20050020,rockchip,rk2928-pwm£  ‘ØG ódisabledÌdefaultÚpwm@20050030,rockchip,rk2928-pwm£ 0‘ØGóokayÌdefaultÚë.i2c@20056000,rockchip,rk3066-i2c£ ` §*+ØRßi2c ódisabledÌdefaultÚi2c@2005a000,rockchip,rk3066-i2c£   §++ØSßi2c ódisabledÌdefaultÚi2c@2005e000,rockchip,rk3066-i2c£ à §4+ØTßi2c ódisabledÌdefaultÚserial@20064000&,rockchip,rk3066-uartsnps,dw-apb-uart£ @ §$¦°ßbaudclkapb_pclkØBNóokay½  ÂtxrxÌdefaultÚserial@20068000&,rockchip,rk3066-uartsnps,dw-apb-uart£ € §%¦°ßbaudclkapb_pclkØCOóokay½  ÂtxrxÌdefaultÚsaradc@2006c000,rockchip,saradc£ À §œØGJßsaradcapb_pclkOW Vsaradc-apb ódisabledspi@20070000,rockchip,rk3066-spiØEHßspiclkapb_pclk §&£ ½ Âtxrx ódisabledÌdefaultÚ !"spi@20074000,rockchip,rk3066-spiØFIßspiclkapb_pclk §'£ @½ Âtxrx ódisabledÌdefaultÚ#$%&cpus®rockchip,rk3066-smpcpu@0¼cpu,arm,cortex-a9È'£8Ù›@Ö O€íØa€*ˆ s€*ˆ 'ÀÈà°ÀÈàÂÀg8êœ@Øø(cpu@1¼cpu,arm,cortex-a9È'£sram@10080000 ,mmio-sram£ œsmp-sram@0,rockchip,rk3066-smp-sram£Pi2s@10118000,rockchip,rk3066-i2s£€  §ÌdefaultÚ)½Âtxrxßi2s_hclki2s_clkØÆK ódisabledi2s@1011a000,rockchip,rk3066-i2s£   § ÌdefaultÚ*½Âtxrxßi2s_hclki2s_clkØÇL ódisabledi2s@1011c000,rockchip,rk3066-i2s£À  §ÌdefaultÚ+½  Âtxrxßi2s_hclki2s_clkØÈM ódisabledclock-controller@20000000,rockchip,rk3066a-cru£ + 9@*ËÔ^ÌÕ_ :ׄ#g¸€á£ðÑ€xhÀá£ðÑ€xhÀëtimer@2000e000,snps,dw-apb-timer-osc£ à §.ØVD ßtimerpclkefuse@20010000,rockchip,rk3066a-efuse£ @Ø[ ßpclk_efusecpu_leakage@17£timer@20038000,snps,dw-apb-timer-osc£ € §,ØTB ßtimerpclktimer@2003a000,snps,dw-apb-timer-osc£   §-ØUC ßtimerpclktsadc@20060000,rockchip,rk3066-tsadc£ Ø]]ßsaradcapb_pclk §œO\ Vsaradc-apb ódisabledphy1,rockchip,rk3066a-usb-phyrockchip,rk3288-usb-phy+ ódisabledusb-phy@17cF£|ØQßphyclk ëusb-phy@188F£ˆØRßphyclk ëpinctrl,rockchip,rk3066a-pinctrl+œgpio0@20034000,rockchip,gpio-bank£ @ §6ØUQa€•gpio1@2003c000,rockchip,gpio-bank£ À §7ØVQa€•gpio2@2003e000,rockchip,gpio-bank£ à §8ØWQa€•gpio3@20080000,rockchip,gpio-bank£  §9ØXQa€•ë/gpio4@20084000,rockchip,gpio-bank£ @ §:ØYQa€•ë0gpio6@2000a000,rockchip,gpio-bank£   §<ØZQa€•ëpcfg_pull_defaultmë-pcfg_pull_noneƒë,emacemac-xfer€,,,,,,,,emac-mdio ,,emmcemmc-clk-emmc-cmd -emmc-rst -i2c0i2c0-xfer ,,ëi2c1i2c1-xfer ,,ëi2c2i2c2-xfer ,,ëi2c3i2c3-xfer ,,ëi2c4i2c4-xfer ,,ëpwm0pwm0-out,ëpwm1pwm1-out,ëpwm2pwm2-out,ëpwm3pwm3-out,ëspi0spi0-clk-ëspi0-cs0-ë"spi0-tx-ë spi0-rx-ë!spi0-cs1-spi1spi1-clk-ë#spi1-cs0-ë&spi1-rx-ë%spi1-tx-ë$spi1-cs1-uart0uart0-xfer --ëuart0-cts-uart0-rts-uart1uart1-xfer --ëuart1-cts-uart1-rts-uart2uart2-xfer - -ëuart3uart3-xfer --ëuart3-cts-uart3-rts-sd0sd0-clk-ë sd0-cmd -ë sd0-cd-ë sd0-wp-sd0-bus-width1 -sd0-bus-width4@ - - - -ë sd1sd1-clk-ësd1-cmd-ësd1-cd-sd1-wp-sd1-bus-width1-sd1-bus-width4@----ëi2s0i2s0-bus-- - - - - ---ë)i2s1i2s1-bus`------ë*i2s2i2s2-bus`------ë+memory@60000000¼memory£`@vdd-log,pwm-regulator ž.èvdd_logOO€gO€&£B@dO€*óokayfixed-regulator,regulator-fixed sdmmc-supplyO-ÆÀg-ÆÀ ±/¶† Çëgpio-keys ,gpio-keysÒpower ÝãtîGPIO Key Powerôdvolume-down Ý0ãrîGPIO Key Vol-ôd #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1rangesreginterrupts#dma-cellsarm,pl330-broken-no-flushpclocksclock-namesphandlestatusclock-frequency#clock-cellsclock-output-namesassigned-clocksassigned-clock-ratesresetsinterrupt-namescache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modefifo-depthreset-namesmax-frequencyvmmc-supplybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpnon-removableoffsetmode-normalmode-recoverymode-bootloadermode-loadervcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu0-supplyrockchip,playback-channelsrockchip,capture-channels#reset-cells#phy-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinspwmsvoltage-tablegpiostartup-delay-usvin-supplyautorepeatgpioslinux,codelabellinux,input-typewakeup-sourcedebounce-interval