Ð þíQ8L8(äL(,haoyu,marsboard-rk3066rockchip,rk3066a7MarsBoard RK3066aliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/dwmmc@1021c000f/dwmmc@10214000l/dwmmc@10218000r/serial@10124000z/serial@10126000‚/serial@20064000Š/serial@20068000’/spi@20070000—/spi@20074000amba ,simple-busœdma-controller@20018000,arm,pl330arm,primecell£ €@§²½ØÀ ßapb_pclkëdma-controller@2001c000,arm,pl330arm,primecell£ À@§²½ØÀ ßapb_pclk ódisableddma-controller@20078000,arm,pl330arm,primecell£ €@§²½ØÁ ßapb_pclkëoscillator ,fixed-clockún6 xin24mgpu@10090000",rockchip,rk3066-maliarm,mali-400£ ØÅÅ ßbuscore*Å:õáOx ódisabledx§5Vgpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3l2-cache-controller@10138000,arm,pl310-cache£€ftë/scu@1013c000,arm,cortex-a9-scu£Àglobal-timer@1013c200,arm,cortex-a9-global-timer£  § Ølocal-timer@1013c600,arm,cortex-a9-twd-timer£Æ  § Øinterrupt-controller@1013d000,arm,cortex-a9-gic€•£ÐÁëserial@10124000&,rockchip,rk3066-uartsnps,dw-apb-uart£@ §"¦°ßbaudclkapb_pclkØ@Lóokay½ÂtxrxÌdefaultÚserial@10126000&,rockchip,rk3066-uartsnps,dw-apb-uart£` §#¦°ßbaudclkapb_pclkØAMóokay½ÂtxrxÌdefaultÚusb@10180000,rockchip,rk3066-usbsnps,dwc2£ §ØÃßotgäotgìþ €€@@  !usb2-phyóokayusb@101c0000 ,snps,dwc2£ §ØÉßotgähost !usb2-phyóokayethernet@10204000,rockchip,rk3066-emac£ @< §+ØÄD ßhclkmacref8dBrmiióokayK O Ìdefault Ú ethernet-phy@0£§ë dwmmc@10214000,rockchip,rk2928-dw-mshc£!@ §ØÀHßbiuciu½Ârx-txZOQeresetóokayúúð€qúð€ÌdefaultÚdwmmc@10218000,rockchip,rk2928-dw-mshc£!€ §ØÁIßbiuciu½Ârx-txZORereset ódisabledÌdefaultÚdwmmc@1021c000,rockchip,rk2928-dw-mshc£!À §ØÂJßbiuciu½Ârx-txZOSereset ódisabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd£ @reboot-mode,syscon-reboot-mode‹@’RBÞRBìRBà ¼RBÃgrf@20008000,syscon£ €ëi2c@2002d000,rockchip,rk3066-i2c£ Ð §(+ßi2cØP ódisabledÌdefaultÚi2c@2002f000,rockchip,rk3066-i2c£ ð §)+ØQßi2cóokayÌdefaultÚú€tps@2d£-§ÈÔàìø ,ti,tps65910regulatorsregulator@0)vcc_rtc8£Lvrtcregulator@1)vcc_io8£Lvioëregulator@2)vdd_arma 'Àyã`‘8£Lvdd1ë0regulator@3)vcc_ddra 'Àyã`‘8£Lvdd2regulator@5 )vcc18_cif8£Lvdig1regulator@6)vdd_118£Lvdig2regulator@7)vcc_258£Lvpllregulator@8)vcc_188£Lvdacregulator@9 )vcc25_hdmi8£ Lvaux1regulator@10)vcca_338£ Lvaux2regulator@11 )vcc_rmii£ Lvaux33ë regulator@12 )vcc28_cif8£ Lvmmcregulator@4£Lvdd3regulator@13£ Lvbbpwm@20030000,rockchip,rk2928-pwm£ £ØF ódisabledÌdefaultÚpwm@20030010,rockchip,rk2928-pwm£ £ØF ódisabledÌdefaultÚwatchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt£ ÀØK §3óokaypwm@20050020,rockchip,rk2928-pwm£  £ØG ódisabledÌdefaultÚ pwm@20050030,rockchip,rk2928-pwm£ 0£ØGóokayÌdefaultÚ!ë6i2c@20056000,rockchip,rk3066-i2c£ ` §*+ØRßi2c ódisabledÌdefaultÚ"i2c@2005a000,rockchip,rk3066-i2c£   §++ØSßi2c ódisabledÌdefaultÚ#i2c@2005e000,rockchip,rk3066-i2c£ à §4+ØTßi2c ódisabledÌdefaultÚ$serial@20064000&,rockchip,rk3066-uartsnps,dw-apb-uart£ @ §$¦°ßbaudclkapb_pclkØBNóokay½ÂtxrxÌdefaultÚ%serial@20068000&,rockchip,rk3066-uartsnps,dw-apb-uart£ € §%¦°ßbaudclkapb_pclkØCOóokay½ ÂtxrxÌdefaultÚ&saradc@2006c000,rockchip,saradc£ À §®ØGJßsaradcapb_pclkOW esaradc-apb ódisabledspi@20070000,rockchip,rk3066-spiØEHßspiclkapb_pclk §&£ ½  Âtxrx ódisabledÌdefaultÚ'()*spi@20074000,rockchip,rk3066-spiØFIßspiclkapb_pclk §'£ @½  Âtxrx ódisabledÌdefaultÚ+,-.cpusÀrockchip,rk3066-smpcpu@0Îcpu,arm,cortex-a9Ú/£8ë›@Ö O€íØa€*ˆ s€*ˆ 'ÀÈà°ÀÈàÂÀg8üœ@Ø 0cpu@1Îcpu,arm,cortex-a9Ú/£sram@10080000 ,mmio-sram£ œsmp-sram@0,rockchip,rk3066-smp-sram£Pi2s@10118000,rockchip,rk3066-i2s£€  §ÌdefaultÚ1½Âtxrxßi2s_hclki2s_clkØÆK1 ódisabledi2s@1011a000,rockchip,rk3066-i2s£   § ÌdefaultÚ2½Âtxrxßi2s_hclki2s_clkØÇL1 ódisabledi2s@1011c000,rockchip,rk3066-i2s£À  §ÌdefaultÚ3½  Âtxrxßi2s_hclki2s_clkØÈM1 ódisabledclock-controller@20000000,rockchip,rk3066a-cru£ + K@*ËÔ^ÌÕ_ :ׄ#g¸€á£ðÑ€xhÀá£ðÑ€xhÀëtimer@2000e000,snps,dw-apb-timer-osc£ à §.ØVD ßtimerpclkefuse@20010000,rockchip,rk3066a-efuse£ @Ø[ ßpclk_efusecpu_leakage@17£timer@20038000,snps,dw-apb-timer-osc£ € §,ØTB ßtimerpclktimer@2003a000,snps,dw-apb-timer-osc£   §-ØUC ßtimerpclktsadc@20060000,rockchip,rk3066-tsadc£ Ø]]ßsaradcapb_pclk §®O\ esaradc-apb ódisabledphy1,rockchip,rk3066a-usb-phyrockchip,rk3288-usb-phy+óokayusb-phy@17cX£|ØQßphyclk ëusb-phy@188X£ˆØRßphyclk ëpinctrl,rockchip,rk3066a-pinctrl+œgpio0@20034000,rockchip,gpio-bank£ @ §6ØUcs€•gpio1@2003c000,rockchip,gpio-bank£ À §7ØVcs€•ëgpio2@2003e000,rockchip,gpio-bank£ à §8ØWcs€•gpio3@20080000,rockchip,gpio-bank£  §9ØXcs€•ë7gpio4@20084000,rockchip,gpio-bank£ @ §:ØYcs€•gpio6@2000a000,rockchip,gpio-bank£   §<ØZcs€•ëpcfg_pull_defaultë5pcfg_pull_none•ë4emacemac-xfer€¢44444444ë emac-mdio ¢44ë emmcemmc-clk¢5emmc-cmd¢ 5emmc-rst¢ 5i2c0i2c0-xfer ¢44ëi2c1i2c1-xfer ¢44ëi2c2i2c2-xfer ¢44ë"i2c3i2c3-xfer ¢44ë#i2c4i2c4-xfer ¢44ë$pwm0pwm0-out¢4ëpwm1pwm1-out¢4ëpwm2pwm2-out¢4ë pwm3pwm3-out¢4ë!spi0spi0-clk¢5ë'spi0-cs0¢5ë*spi0-tx¢5ë(spi0-rx¢5ë)spi0-cs1¢5spi1spi1-clk¢5ë+spi1-cs0¢5ë.spi1-rx¢5ë-spi1-tx¢5ë,spi1-cs1¢5uart0uart0-xfer ¢55ëuart0-cts¢5uart0-rts¢5uart1uart1-xfer ¢55ëuart1-cts¢5uart1-rts¢5uart2uart2-xfer ¢5 5ë%uart3uart3-xfer ¢55ë&uart3-cts¢5uart3-rts¢5sd0sd0-clk¢5ësd0-cmd¢ 5ësd0-cd¢5ësd0-wp¢5sd0-bus-width1¢ 5sd0-bus-width4@¢ 5 5 5 5ësd1sd1-clk¢5ësd1-cmd¢5ësd1-cd¢5ësd1-wp¢5sd1-bus-width1¢5sd1-bus-width4@¢5555ëi2s0i2s0-bus¢55 5 5 5 5 555ë1i2s1i2s1-bus`¢555555ë2i2s2i2s2-bus`¢555555ë3lan8720aphy-int¢4ë memory@60000000Îmemory£`@vdd-log,pwm-regulator °6è)vdd_logaO€yO€8µB@dO€*óokaysdmmc-regulator,regulator-fixed )sdmmc-supplya-ÆÀy-ÆÀ Ã7Ȇ Ùëvsys-regulator,regulator-fixed)vsysaLK@yLK@‘ë #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1rangesreginterrupts#dma-cellsarm,pl330-broken-no-flushpclocksclock-namesphandlestatusclock-frequency#clock-cellsclock-output-namesassigned-clocksassigned-clock-ratesresetsinterrupt-namescache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modephyphy-supplyfifo-depthreset-namesmax-frequencyvmmc-supplyoffsetmode-normalmode-recoverymode-bootloadermode-loadervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu0-supplyrockchip,playback-channelsrockchip,capture-channels#reset-cells#phy-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinspwmsvoltage-tablegpiostartup-delay-usvin-supply