Š žķJhHD”(ŌDL+Altera SOCFPGA Arria V SoC Development Kit!!altr,socfpga-arria5altr,socfpgaaliases,/soc/ethernet@ff7020006/soc/ethernet@ff702000@/soc/serial0@ffc02000H/soc/serial1@ffc03000P/soc/timer0@ffc08000W/soc/timer1@ffc09000^/soc/timer2@ffd00000e/soc/timer3@ffd01000cpuslaltr,socfpga-smpcpu@0!arm,cortex-a9zcpu†Š›cpu@1!arm,cortex-a9zcpu†Š›pmu@ff111000!arm,cortex-a9-pmu£“°±æ†’’0intc@fffed000!arm,cortex-a9-gicŅ憒žŠ’žĮ›soc !simple-buszsoc£ųamba !simple-busųpdma@ffe01000!arm,pl330arm,primecell†’ą`“hijklmno’  & -apb_pclk›1base_fpga_region !fpga-region9can@ffc00000 !bosch,d_can†’Ą0“ƒ„…†& Bdisabledcan@ffc01000 !bosch,d_can†’Ą0“‡ˆ‰Š& Bdisabledclkmgr@ffd04000 !altr,clk-mgr†’Š@clocksosc1I !fixed-clockV}x@› osc2I !fixed-clock› f2s_periph_ref_clkI !fixed-clock› f2s_sdram_ref_clkI !fixed-clock›main_pll@40I!altr,socfpga-pll-clock& †@› mpuclk@48I!altr,socfpga-perip-clk&  fą †H›mainclk@4cI!altr,socfpga-perip-clk&  fä †L›dbg_base_clk@50I!altr,socfpga-perip-clk&  fč †P›main_qspi_clk@54I!altr,socfpga-perip-clk& †T›main_nand_sdmmc_clk@58I!altr,socfpga-perip-clk& †X›cfg_h2f_usr0_clk@5cI!altr,socfpga-perip-clk& †\›periph_pll@80I!altr,socfpga-pll-clock & †€› emac0_clk@88I!altr,socfpga-perip-clk& †ˆ›emac1_clk@8cI!altr,socfpga-perip-clk& †Œ›per_qsi_clk@90I!altr,socfpga-perip-clk& †›per_nand_mmc_clk@94I!altr,socfpga-perip-clk& †”›per_base_clk@98I!altr,socfpga-perip-clk& †˜›h2f_usr1_clk@9cI!altr,socfpga-perip-clk& †œ›sdram_pll@c0I!altr,socfpga-pll-clock & †Ą›ddr_dqs_clk@c8I!altr,socfpga-perip-clk&†Č›ddr_2x_dqs_clk@ccI!altr,socfpga-perip-clk&†Ģ› ddr_dq_clk@d0I!altr,socfpga-perip-clk&†Š›!h2f_usr2_clk@d4I!altr,socfpga-perip-clk&†Ō›"mpu_periph_clkI!altr,socfpga-perip-clk&n›0mpu_l2_ram_clkI!altr,socfpga-perip-clk&nl4_main_clkI!altr,socfpga-gate-clk&|`›l3_main_clkI!altr,socfpga-perip-clk&nl3_mp_clkI!altr,socfpga-gate-clk& fd|`›l3_sp_clkI!altr,socfpga-gate-clk& fdl4_mp_clkI!altr,socfpga-gate-clk& fd|`›'l4_sp_clkI!altr,socfpga-gate-clk& fd|`›(dbg_at_clkI!altr,socfpga-gate-clk& fh|`›dbg_clkI!altr,socfpga-gate-clk& fh|`dbg_trace_clkI!altr,socfpga-gate-clk& fl|`dbg_timer_clkI!altr,socfpga-gate-clk&|`cfg_clkI!altr,socfpga-gate-clk&|`h2f_user0_clkI!altr,socfpga-gate-clk&|` emac_0_clkI!altr,socfpga-gate-clk&| ›%emac_1_clkI!altr,socfpga-gate-clk&| ›&usb_mp_clkI!altr,socfpga-gate-clk&|  f¤›2spi_m_clkI!altr,socfpga-gate-clk&|  f¤›/can0_clkI!altr,socfpga-gate-clk&|  f¤›can1_clkI!altr,socfpga-gate-clk&|  f¤ ›gpio_db_clkI!altr,socfpga-gate-clk&|  fØh2f_user1_clkI!altr,socfpga-gate-clk&| sdmmc_clkI!altr,socfpga-gate-clk & | …‡›sdmmc_clk_dividedI!altr,socfpga-gate-clk&| n›*nand_x_clkI!altr,socfpga-gate-clk & |  ›,nand_clkI!altr,socfpga-gate-clk & |  nqspi_clkI!altr,socfpga-gate-clk & |  ›-ddr_dqs_clk_gateI!altr,socfpga-gate-clk&|Ųddr_2x_dqs_clk_gateI!altr,socfpga-gate-clk& |Ųddr_dq_clk_gateI!altr,socfpga-gate-clk&!|Ųh2f_user2_clkI!altr,socfpga-gate-clk&"|Ųfpga_bridge@ff400000!altr,socfpga-lwhps2fpga-bridge†’@#a&fpga_bridge@ff500000!altr,socfpga-hps2fpga-bridge†’P#`&fpgamgr@ff706000!altr,socfpga-fpga-mgr†’p`’¹ “Æ›ethernet@ff7000000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac –$`†’p  “s©macirq¹&% -stmmaceth#  ÅstmmacethŃģ€ Bdisabledethernet@ff7020000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmac –$`†’p  “x©macirq¹&& -stmmaceth#! ÅstmmacethŃģ€Bokay$rgmii-:GTan (z‡Šgpio@ff708000!snps,dw-apb-gpio†’p€&'Bokaygpio-controller@0!snps,dw-apb-gpio-port“£Æ†ćŅ “¤›4gpio@ff709000!snps,dw-apb-gpio†’p&'Bokaygpio-controller@0!snps,dw-apb-gpio-port“£Æ†ćŅ “„›5gpio@ff70a000!snps,dw-apb-gpio†’p &'Bokaygpio-controller@0!snps,dw-apb-gpio-port“£Æ†ćŅ “¦i2c@ffc04000!snps,designware-i2c†’Ą@#,&( “žBokayV† ½ˆÕˆeeprom@51 !atmel,24c32†Qķ rtc@68!dallas,ds1339†hi2c@ffc05000!snps,designware-i2c†’ĄP#-&( “Ÿ Bdisabledi2c@ffc06000!snps,designware-i2c†’Ą`#.&( “  Bdisabledi2c@ffc07000!snps,designware-i2c†’Ąp#/&( “” Bdisabledeccmgr!altr,socfpga-ecc-managerųl2-ecc@ffd08140!altr,socfpga-l2-ecc†’Š@“$%ocram-ecc@ffd08144!altr,socfpga-ocram-ecc†’ŠDö)“²³cache-controller@fffef000!arm,pl310-cache†’žš “&ū   %6DSg{”­æ›l3regs@0xff800000!altr,l3regssyscon†’€dwmmc0@ff704000!altr,socfpga-dw-mshc†’p@ “‹ &'*-biuciuBokayÓŻēł ++nand@ff900000!altr,socfpga-denali-nand†’’ø#nand_datadenali_reg “-’’’’&, Bdisabledsram@ffff0000 !mmio-sram†’’›)spi@ff705000!cdns,qspi-nor†’pP’  “—6€FV&-Bokayflash@0!micron,n25q256ajedec,spi-nor†kõį}Œ›«»2É2×åpartition@qspi-bootóFlash 0 Raw Data†€partition@qspi-rootfsóFlash 0 jffs2 Filesystem†€€rstmgr@ffd05000ł !altr,rst-mgr†’ŠP›#snoop-control-unit@fffec000!arm,cortex-a9-scu†’žĄsdr@ffc25000!altr,sdr-ctlsyscon†’ĀP›.sdramedac!altr,sdram-edac. “'spi@fff00000!snps,dw-apb-ssi†’š “š)&/ Bdisabledspi@fff01000!snps,dw-apb-ssi†’š “›)&/ Bdisabledsysmgr@ffd08000!altr,sys-mgrsyscon†’Š€@0’Š€Ä›$timer@fffec600!arm,cortex-a9-twd-timer†’žĘ “ &0timer0@ffc08000!snps,dw-apb-timer “§†’Ą€&(-timertimer1@ffc09000!snps,dw-apb-timer “؆’Ą&(-timertimer2@ffd00000!snps,dw-apb-timer “©†’Š& -timertimer3@ffd01000!snps,dw-apb-timer “Ŗ†’Š& -timerserial0@ffc02000!snps,dw-apb-uart†’Ą  “¢@J&(W11\txrxserial1@ffc03000!snps,dw-apb-uart†’Ą0 “£@J&(W11\txrxusbphyf!usb-nop-xceivBokay›3usb@ffb00000 !snps,dwc2†’°’’ “}&2-otg#"Ådwc2q3 vusb2-phy Bdisabledusb@ffb40000 !snps,dwc2†’“’’ “€&2-otg##Ådwc2q3 vusb2-phyBokaywatchdog@ffd02000 !snps,dw-wdt†’Š  “«& Bokaywatchdog@ffd03000 !snps,dw-wdt†’Š0 “¬&  Bdisabledchosen €earlyprintk‰serial0:115200n8memory@0zmemory†@leds !gpio-ledshps0 óhps_led0 ·4hps1 óhps_led1 ·5 hps2 óhps_led2 ·4hps3 óhps_led3 ·43-3-v-regulator!regulator-fixed•3.3V¤2Z ¼2Z ›+ #address-cells#size-cellsmodelcompatibleethernet0ethernet1serial0serial1timer0timer1timer2timer3enable-methoddevice_typeregnext-level-cachephandleinterrupt-parentinterruptsinterrupt-affinity#interrupt-cellsinterrupt-controllerranges#dma-cells#dma-channels#dma-requestsclocksclock-namesfpga-mgrstatus#clock-cellsclock-frequencydiv-regfixed-dividerclk-gateclk-phaseresetsaltr,sysmgr-sysconinterrupt-namesmac-addressreset-namessnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthrx-fifo-depthphy-moderxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-pstxen-skew-pstxc-skew-psrxdv-skew-psrxc-skew-psgpio-controller#gpio-cellssnps,nr-gpiosi2c-sda-falling-time-nsi2c-scl-falling-time-nspagesizeiramcache-unifiedcache-levelarm,tag-latencyarm,data-latencyprefetch-dataprefetch-instrarm,shared-overridearm,double-linefillarm,double-linefill-incrarm,double-linefill-wraparm,prefetch-droparm,prefetch-offsetbroken-cdbus-widthcap-mmc-highspeedcap-sd-highspeedvmmc-supplyvqmmc-supplyreg-namesdma-maskcdns,fifo-depthcdns,fifo-widthcdns,trigger-addressspi-max-frequencym25p,fast-readcdns,page-sizecdns,block-sizecdns,read-delaycdns,tshsl-nscdns,tsd2d-nscdns,tchsh-nscdns,tslch-nslabel#reset-cellsaltr,modrst-offsetaltr,sdr-sysconnum-cscpu1-start-addrreg-shiftreg-io-widthdmasdma-names#phy-cellsphysphy-namesbootargsstdout-pathregulator-nameregulator-min-microvoltregulator-max-microvolt