[P8WX(W ),Allwinner A31 APP4 EVB1 Evaluation Board(2allwinner,app4-evb1allwinner,sun6i-a31chosen=Dserial0:115200n8framebuffer@002allwinner,simple-framebuffersimple-framebufferPde_be0-lcd0-hdmi@c3/2wz jdisabledframebuffer@102allwinner,simple-framebuffersimple-framebuffer Pde_be0-lcd00c3/wz jdisabledaliasesq/soc@1c00000/ethernet@1c30000{/soc@1c00000/serial@1c28000memorymemory@timer2arm,armv7-timer0   n6cpusallwinner,sun6i-a31cpu@02arm,cortex-a7cpuc aO /O SB@cpu@12arm,cortex-a7cpuc aO /O SB@cpu@22arm,cortex-a7cpuc aO /O SB@cpu@32arm,cortex-a7cpuc aO /O SB@thermal-zonescpu_thermal,:cooling-mapsmap0J Otripscpu_alert0^pjpassivecpu_crit^j criticalpmu2arm,cortex-a7-pmu0xyz{clocks=osc24Mu 2fixed-clockn6clk@0u 2fixed-clockosc32kclk@1u 2fixed-clock}x@ mii_phy_txclk@2u 2fixed-clocksY@ gmac_int_txclk@1c200d0u2allwinner,sun7i-a20-gmac-clkcgmac_txdisplay-engine#2allwinner,sun6i-a31-display-engine  jdisabledsoc@1c00000 2simple-bus=dma-controller@1c020002allwinner,sun6i-a31-dma  2clcd-controller@1c0c0002allwinner,sun6i-a31-tcon Vlcdc/ahbtcon-ch0tcon-ch1tcon0-pixel-clockportsport@0endpoint@0 'endpoint@1 !port@1endpoint@1 lcd-controller@1c0d0002allwinner,sun6i-a31-tcon Wlcdc0ahbtcon-ch0tcon-ch1tcon1-pixel-clockportsport@0endpoint@0 (endpoint@1"port@1endpoint@1mmc@1c0f0002allwinner,sun7i-a20-mmc cOQPahbmmcoutputsampleahb < jdisabledmmc@1c100002allwinner,sun7i-a20-mmc cRTSahbmmcoutputsampleahb = jdisabledmmc@1c110002allwinner,sun7i-a20-mmc cUWVahbmmcoutputsampleahb > jdisabledmmc@1c120002allwinner,sun7i-a20-mmc  cXZYahbmmcoutputsample ahb ? jdisabledhdmi@1c160002allwinner,sun6i-a31-hdmi` X(c2 ahbmodddcpll-0pll-1ahbddc-txddc-rxaudio-tx   jdisabledportsport@0endpoint@0 endpoint@1port@1usb@1c190002allwinner,sun6i-a31-musbc( G mcusb( jdisabledphy@1c194002allwinner,sun6i-a31-usb-phy/phy_ctrlpmu1pmu2cdefusb0_phyusb1_phyusb2_phy!usb0_resetusb1_resetusb2_resetjokay9Dusb@1c1a000&2allwinner,sun6i-a31-ehcigeneric-ehci Hc)usbjokayusb@1c1a400&2allwinner,sun6i-a31-ohcigeneric-ohci Ic+gusb jdisabledusb@1c1b000&2allwinner,sun6i-a31-ehcigeneric-ehci Jc*usb jdisabledusb@1c1b400&2allwinner,sun6i-a31-ohcigeneric-ohci Kc,husb jdisabledusb@1c1c400&2allwinner,sun6i-a31-ohcigeneric-ohci Mc-i jdisabledclock@1c200002allwinner,sun6i-a31-ccuc hoscloscuUpinctrl@1c208002allwinner,sun6i-a31-pinctrl0 c@apbhoscloscbr0gmac_gmii@0PA0PA1PA2PA3PA4PA5PA6PA7PA8PA9PA10PA11PA12PA13PA14PA15PA16PA17PA18PA19PA20PA21PA22PA23PA24PA25PA26PA27gmacgmac_mii@0TPA0PA1PA2PA3PA8PA9PA11PA12PA13PA14PA19PA20PA21PA22PA23PA24PA26PA27gmacgmac_rgmii@0FPA0PA1PA2PA3PA9PA10PA11PA12PA13PA14PA19PA20PA25PA26PA27gmac(i2c0@0 PH14PH15i2c0i2c1@0 PH16PH17i2c1i2c2@0 PH18PH19i2c2lcd0_rgb888PD0PD1PD2PD3PD4PD5PD6PD7PD8PD9PD10PD11PD12PD13PD14PD15PD16PD17PD18PD19PD20PD21PD22PD23PD24PD25PD26PD27lcd0mmc0@0PF0PF1PF2PF3PF4PF5mmc0mmc1@0PG0PG1PG2PG3PG4PG5mmc1mmc2@0PC6PC7PC8PC9PC10PC11mmc2mmc2@13PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15PC24mmc2mmc3@13PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15PC24mmc3(spdif@0PH28spdifuart0@0 PH20PH21uart0usb1_vbus_pin@0PH27 gpio_out1timer@1c20c002allwinner,sun4i-a10-timer <cwatchdog@1c20ca02allwinner,sun6i-a31-wdt spdif@1c210002allwinner,sun6i-a31-spdif c>c+ apbspdifrxtx jdisabledi2s@1c220002allwinner,sun6i-a31-i2s  cAa-apbmodrxtx jdisabledi2s@1c224002allwinner,sun6i-a31-i2s$ cBb.apbmodrxtx jdisabledlradc@1c228002allwinner,sun4i-a10-lradc-keys(  jdisabledrtp@1c250002allwinner,sun6i-a31-tsP serial@1c280002snps,dw-apb-uart€ cG3rxtxjokay defaultserial@1c284002snps,dw-apb-uart„ cH4rxtx jdisabledserial@1c288002snps,dw-apb-uartˆ cI5rxtx jdisabledserial@1c28c002snps,dw-apb-uartŒ cJ6  rxtx jdisabledserial@1c290002snps,dw-apb-uart cK7  rxtx jdisabledserial@1c294002snps,dw-apb-uart” cL8rxtx jdisabledi2c@1c2ac002allwinner,sun6i-a31-i2c¬ cC/ jdisabledi2c@1c2b0002allwinner,sun6i-a31-i2c° cD0 jdisabledi2c@1c2b4002allwinner,sun6i-a31-i2c´ cE1 jdisabledi2c@1c2b8002allwinner,sun6i-a31-i2c¸ cF2 jdisabledethernet@1c300002allwinner,sun7i-a20-gmacT R macirq c!stmmacethallwinner_gmac_tx  stmmaceth$-> jdisabledcrypto-engine@1c1500062allwinner,sun6i-a31-cryptoallwinner,sun4i-a10-cryptoP Pc\ahbmodahbcodec@1c22c002allwinner,sun6i-a31-codec, c= apbcodec*rxtx jdisabledtimer@1c6000082allwinner,sun6i-a31-hstimerallwinner,sun7i-a20-hstimer03456c#spi@1c680002allwinner,sun6i-a31-spiƀ Ac$]ahbmodrxtx jdisabledspi@1c690002allwinner,sun6i-a31-spiƐ Bc%^ahbmodrxtx jdisabledspi@1c6a0002allwinner,sun6i-a31-spiƠ Cc&_ahbmodrxtx jdisabledspi@1c6b0002allwinner,sun6i-a31-spiư Dc'`ahbmodrxtx jdisabledinterrupt-controller@1c81000%2arm,cortex-a7-gicarm,cortex-a15-gic  @ ` r  display-frontend@1e00000%2allwinner,sun6i-a31-display-frontend ]c5|u ahbmodram!portsport@1endpoint@0#endpoint@1display-frontend@1e20000%2allwinner,sun6i-a31-display-frontend ^c6}v ahbmodram" portsport@1endpoint@0$endpoint@1display-backend@1e40000$2allwinner,sun6i-a31-display-backend `c4{x ahbmodram U{eportsport@0endpoint@0endpoint@1port@1endpoint@1 drc@1e500002allwinner,sun6i-a31-drc [c<r ahbmodram(Ueportsport@0endpoint@1 port@1endpoint@0! endpoint@1"display-backend@1e60000$2allwinner,sun6i-a31-display-backend _c3zw ahbmodramUzeportsport@0endpoint@0#endpoint@1$port@1endpoint@0%&drc@1e700002allwinner,sun6i-a31-drc [c;q ahbmodram'Ueportsport@0endpoint@0&%port@1endpoint@0' endpoint@1( rtc@1f000002allwinner,sun6i-a31-rtcT()interrupt-controller@1f00c002allwinner,sun6i-a31-r-intcr  prcm@1f014002allwinner,sun6i-a31-prcmar100_clk2allwinner,sun6i-a31-ar100-clkuc  ar100)ahb0_clk2fixed-factor-clockuzc)ahb0*apb0_clk2allwinner,sun6i-a31-apb0-clkuc*apb0+apb0_gates_clk#2allwinner,sun6i-a31-apb0-gates-clkuc+Dapb0_pioapb0_irapb0_timerapb0_p2wiapb0_uartapb0_1wireapb0_i2c,ir_clku2allwinner,sun4i-a10-mod0-clkcir-apb0_rst 2allwinner,sun6i-a31-clock-resetU.cpucfg@1f01c002allwinner,sun6i-a31-cpuconfigir@1f020002allwinner,sun5i-a13-ir c,-apbir. % @ jdisabledpinctrl@1f02c002allwinner,sun6i-a31-r-pinctrl,-.c,apbhosclosc.brir@0PL4s_irp2wiPL0PL1s_p2wi/i2c@1f034002allwinner,sun6i-a31-p2wi4 'c,. default/ jdisabledahci-5v2regulator-fixedahci-5vLK@LK@0 jdisabledusb0-vbus2regulator-fixed usb0-vbusLK@LK@0  jdisabledusb1-vbus2regulator-fixed usb1-vbusLK@LK@0jokay1usb2-vbus2regulator-fixed usb2-vbusLK@LK@0 jdisabledvcc3v02regulator-fixedvcc3v0--vcc3v32regulator-fixedvcc3v32Z2Zvcc5v02regulator-fixedvcc5v0LK@LK@ #address-cells#size-cellsinterrupt-parentmodelcompatiblerangesstdout-pathallwinner,pipelineclocksstatusethernet0serial0device_typereginterruptsclock-frequencyarm,cpu-registers-not-fw-configuredenable-methodclock-latencyoperating-points#cooling-cellsphandlepolling-delay-passivepolling-delaythermal-sensorstripcooling-devicetemperaturehysteresis#clock-cellsclock-output-namesallwinner,pipelinesresets#dma-cellsreset-namesclock-namesremote-endpointallwinner,tcon-channeldma-namesdmasinterrupt-namesphysphy-namesextconreg-names#phy-cellsusb1_vbus-supply#reset-cellsgpio-controllerinterrupt-controller#interrupt-cells#gpio-cellspinsfunctiondrive-strengthbias-pull-up#sound-dai-cells#thermal-sensor-cellsreg-shiftreg-io-widthpinctrl-namespinctrl-0snps,pblsnps,fixed-burstsnps,force_sf_dma_modeassigned-clocksassigned-clock-ratesclock-divclock-multregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onenable-active-highgpio