Ð þí?38<(+;Ð,Banana Pi BPI-M2-Ultra*2sinovoip,bpi-m2-ultraallwinner,sun8i-r40clocks=osc24MD 2fixed-clockQn6aosc24Mtosc32kD 2fixed-clockQ€aosc32ktcpuscpu@02arm,cortex-a7|cpuˆcpu@12arm,cortex-a7|cpuˆcpu@22arm,cortex-a7|cpuˆcpu@32arm,cortex-a7|cpuˆdisplay-engine#2allwinner,sun8i-r40-display-engineŒ okaysoc 2simple-bus=clock@100000072allwinner,sun8i-r40-de2-clkallwinner,sun8i-h3-de2-clkˆ§Œ<®modbusº$DÁtmixer@1100000 2allwinner,sun8i-r40-de2-mixer-0ˆ§®busmodºtportsport@1ˆendpointÎtmixer@1200000 2allwinner,sun8i-r40-de2-mixer-1ˆ §®busmodºtportsport@1ˆendpointÎtinterrupt-controller@1c000302allwinner,sun7i-a20-sc-nmiÞóˆÀ0  tmmc@1c0f00012allwinner,sun8i-r40-mmcallwinner,sun50i-a64-mmcˆÀð§ k®ahbmmcºahb%default   okay3 ?I  Rmmc@1c1000012allwinner,sun8i-r40-mmcallwinner,sun50i-a64-mmcˆÁ§!l®ahbmmcº ahb ! okay%default 3 ^ k?vmmc@1c1100032allwinner,sun8i-r40-emmcallwinner,sun50i-a64-emmcˆÁ§"m®ahbmmcº ahb%default " okay3 ^ ?vmmc@1c1200012allwinner,sun8i-r40-mmcallwinner,sun50i-a64-mmcˆÁ §#n®ahbmmcº ahb #  disabledphy@1c134002allwinner,sun8i-r40-usb-phy ˆÁ4ÁHÁ˜ÁÈ„phy_ctrlpmu0pmu1pmu2§|}~®usb0_phyusb1_phyusb2_phyº!usb0_resetusb1_resetusb2_reset okayŽ™ªtusb@1c19000&2allwinner,sun8i-r40-ehcigeneric-ehciˆÁ L§0º»Àusb okayusb@1c19400&2allwinner,sun8i-r40-ohcigeneric-ohciˆÁ” @§3€º»Àusb okayusb@1c1c000&2allwinner,sun8i-r40-ehcigeneric-ehciˆÁÀ N§1º»Àusb okayusb@1c1c400&2allwinner,sun8i-r40-ohcigeneric-ohciˆÁÄ A§4º»Àusb okayclock@1c200002allwinner,sun8i-r40-ccuˆÂ§ ®hoscloscDÁtpinctrl@1c208002allwinner,sun8i-r40-pinctrlˆÂ §O®apbhoscloscÊÞóÚt gmac-rgmii-pinsBæPA0PA1PA2PA3PA4PA5PA6PA7PA8PA10PA11PA12PA13PA15PA16ëgmacô(ti2c0-pinsæPB0PB1ëi2c0tmmc0-pinsæPF0PF1PF2PF3PF4PF5ëmmc0ôtmmc1-pg-pinsæPG0PG1PG2PG3PG4PG5ëmmc1ôt mmc2-pins7æPC5PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15PC24ëmmc2ôtuart0-pb-pins æPB22PB23ëuart0twatchdog@1c20c902allwinner,sun4i-a10-wdtˆ serial@1c280002snps,dw-apb-uartˆ€ §`ºI okay%defaultserial@1c284002snps,dw-apb-uartˆ„ §aºJ  disabledserial@1c288002snps,dw-apb-uartˆˆ §bºK  disabledserial@1c28c002snps,dw-apb-uartˆÂŒ §cºL  disabledserial@1c290002snps,dw-apb-uartˆÂ §dºM  disabledserial@1c294002snps,dw-apb-uartˆ” §eºN  disabledserial@1c298002snps,dw-apb-uartˆ˜ §fºO  disabledserial@1c29c002snps,dw-apb-uartˆÂœ §gºP  disabledi2c@1c2ac002allwinner,sun6i-a31-i2cˆ¬ §Wº@%default okaypmic@342x-powers,axp221ˆ4Þóac-power-supply 2x-powers,axp221-ac-power-supply  disabledadc2x-powers,axp221-adc'battery-power-supply%2x-powers,axp221-battery-power-supply  disabledregulators9 ¸dcdc1Lvcc-3v3[o2Z ‡2Z t dcdc2Lvdd-cpu[oB@‡Ö dcdc3Lvdd-sys[oB@‡Ö dcdc4Ldcdc4dcdc5 Lvcc-dram[oã`‡ã`dc1sw Lvcc-gmac-phyo2Z ‡2Z tdc5ldoLdc5ldoaldo1Laldo1aldo2Lvcc-pa[o&% ‡&% aldo3Lavcc[o)2à‡2Z dldo1 Lvcc-wifi-ioow@‡2Z t dldo2 Lvcc-wifio2Z ‡2Z t dldo3Ldldo3dldo4Ldldo4eldo1Leldo1eldo2Leldo2eldo3Leldo3ldo_io0Lldo_io0  disabledldo_io1Lldo_io1  disabledrtc_ldo[o-ÆÀ‡-ÆÀLrtc_ldodrivevbus Ldrivevbus  disabledusb_power_supply!2x-powers,axp221-usb-power-supply  disabledi2c@1c2b0002allwinner,sun6i-a31-i2cˆ° §XºA  disabledi2c@1c2b4002allwinner,sun6i-a31-i2cˆ´  §YºB  disabledi2c@1c2b8002allwinner,sun6i-a31-i2cˆ¸ X§ZºC  disabledi2c@1c2c0002allwinner,sun6i-a31-i2cˆÂÀ Y§_ºH  disabledethernet@1c500002allwinner,sun8i-r40-gmacŸˆÅ U¦macirqº( stmmaceth§@ ®stmmaceth okay%default¶ Árgmii-idÊmdio2snps,dwmac-mdioethernet-phy@12ethernet-phy-ieee802.3-c22ˆttcon-top@1c700002allwinner,sun8i-r40-tcon-topˆÇ0§K‘žœ$®bustcon-tv0tve0tcon-tv1tve1dsi'atcon-top-tv0tcon-top-tv1tcon-top-dsiº3Dt#portsport@0ˆendpoint@0ˆÎtport@1ˆendpoint@0ˆendpoint@1ˆendpoint@2ˆÎt$endpoint@3ˆÎt'port@2ˆendpoint@1ˆÎtport@3ˆendpoint@0ˆendpoint@1ˆendpoint@2ˆÎt%endpoint@3ˆÎt(port@4ˆendpoint@0ˆÎ t&endpoint@1ˆÎ!t)port@5ˆendpointÎ"t+lcd-controller@1c730002allwinner,sun8i-r40-tcon-tvˆÇ0 3§I# ®ahbtcon-ch1º1lcd okayportsport@0ˆendpoint@0ˆÎ$tendpoint@1ˆÎ%tport@1ˆendpoint@1ˆÎ&t lcd-controller@1c740002allwinner,sun8i-r40-tcon-tvˆÇ@ 4§J# ®ahbtcon-ch1º2lcd  disabledportsport@0ˆendpoint@0ˆÎ'tendpoint@1ˆÎ(tport@1ˆendpoint@1ˆÎ)t!interrupt-controller@1c81000 2arm,gic-400 ˆÈÈ È@ È` Þó  thdmi@1ee000092allwinner,sun8i-r40-dw-hdmiallwinner,sun8i-a83t-dw-hdmiˆî :§;š™®iahbisfrtmdsº#ctrl»* Àhdmi-phy okayportsport@0ˆendpointÎ+t"port@1ˆendpointÎ,t-hdmi-phy@1ef00002allwinner,sun8i-r40-hdmi-phyˆï §:š®busmodpll-0pll-1º"phyŽt*timer2arm,armv7-timer0   aliasesÕ/soc/ethernet@1c50000ß/soc/serial@1c28000chosençserial0:115200n8connector2hdmi-connectorƒaportendpointÎ-t,leds 2gpio-ledspwr-ledóbananapi:red:pwrL ùonuser-led-greenóbananapi:green:userL user-led-blueóbananapi:blue:userL vcc5v02regulator-fixedLvcc5v0oLK@‡LK@  twifi_pwrseq2mmc-pwrseq-simple  t #address-cells#size-cellsinterrupt-parentmodelcompatibleranges#clock-cellsclock-frequencyclock-output-namesphandledevice_typeregallwinner,pipelinesstatusclocksclock-namesresets#reset-cellsremote-endpointinterrupt-controller#interrupt-cellsinterruptsreset-namespinctrl-0pinctrl-namesvmmc-supplybus-widthcd-gpioscd-invertedvqmmc-supplymmc-pwrseqnon-removablereg-names#phy-cellsusb1_vbus-supplyusb2_vbus-supplyphysphy-namesgpio-controller#gpio-cellspinsfunctiondrive-strengthbias-pull-upreg-shiftreg-io-width#io-channel-cellsx-powers,dcdc-freqregulator-nameregulator-always-onregulator-min-microvoltregulator-max-microvoltsysconinterrupt-namesphy-handlephy-modephy-supplyethernet0serial0stdout-pathlabeldefault-stategpioenable-active-highreset-gpios