8( +hisilicon,hi3660-hikey960hisilicon,hi3660 + 7HiKey960psci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D cpu@0arm,cortex-a53HcpuTXpscif w P ncpu@1arm,cortex-a53HcpuTXpscif w P cpu@2arm,cortex-a53HcpuTXpscif w P cpu@3arm,cortex-a53HcpuTXpscif w P cpu@100arm,cortex-a73HcpuTXpscifw &cpu@101arm,cortex-a73HcpuTXpscifw cpu@102arm,cortex-a73HcpuTXpscifw cpu@103arm,cortex-a73HcpuTXpscifw  idle-statespscicpu-sleep-0arm,idle-state,< cluster-sleep-0arm,idle-state,@<  cpu-sleep-1arm,idle-state,&<cluster-sleep-1arm,idle-state , T< l2-cache0cache l2-cache1cacheopp_table0operating-points-v2Mopp00X@_ `mopp01X;_ 5mopp02XSҀ_ mopp03XeE@_B@mopp04Xm5_mopp_table1operating-points-v2Mopp10X5ү_ `mopp11XT@_ 5mopp12Xk@_ mopp13X}_B@mopp14XB_minterrupt-controller@e82b0000 arm,gic-400@T++ +@ +` ~  a53-pmuarm,cortex-a53-pmu0a73-pmuarm,cortex-a73-pmu0 timerarm,armv8-timer 0   soc simple-bus+crg_ctrl@fff35000 hisilicon,hi3660-crgctrlsysconTPcrg_rst_controllerhisilicon,hi3660-resetpctrl@e8a09000hisilicon,hi3660-pctrlsysconT蠐 Mcrg_ctrl@fff34000 hisilicon,hi3660-pmuctrlsysconT@sctrl@fff0a000hisilicon,hi3660-sctrlsysconT9iomcu@ffd7e000hisilicon,hi3660-iomcusysconTresethisilicon,hi3660-resetmailbox@e896b000hisilicon,hi3660-mboxT薰stub_clock@e896b500hisilicon,hi3660-stub-clkT薵  timer@fff14000arm,sp804arm,primecellT@01   timer1timer2apb_pclki2c@ffd71000snps,designware-i2cT v+ " )default7AokayHLS-I2C0i2c@ffd72000snps,designware-i2cT  w+ " )default7Aokayrt1711h@4erichtek,rt1711hTNAokay )default7connectorusb-c-connectorHUSB-CNdualXdualcsinkr2~2Adports+port@1TendpointPport+endpoint@0TOadv7533@39Aokay adi,adv7533T9ports+port@0Tport@1Ti2c@fdf0c000snps,designware-i2cT Q+7 "x)default7 ! Adisabledi2c@fdf0b000snps,designware-i2cT :+6 "`)default7"#AokayHLS-I2C1serial@fdf02000arm,pl011arm,primecellT  Jhuartclkapb_pclk)default7$% Adisabledserial@fdf00000arm,pl011arm,primecellT Krxtx&&99uartclkapb_pclk)default7'( Adisabledserial@fdf03000arm,pl011arm,primecellT0 Lrxtx&&:uartclkapb_pclk)default7)* Adisabledserial@ffd74000arm,pl011arm,primecellT@ ruartclkapb_pclk)default7+,Aokay HLS-UART0serial@fdf01000arm,pl011arm,primecellT Mrxtx&&;;uartclkapb_pclk)default7-.Aokaybluetooth ti,wl1837-st /-serial@fdf05000arm,pl011arm,primecellTP Nrxtx&& <<uartclkapb_pclk)default701 Adisabledserial@fff32000arm,pl011arm,primecellT  O uartclkapb_pclk)default723Aokay HLS-UART1dma@fdf30000hisilicon,k3-dma-1.0T  > hi3660_dma&dma-controller@e804b000hisilicon,hisi-pcm-asp-dma-1.0T   (asp_dma_irqrtc@fff04000arm,pl031arm,primecellT@ . apb_pclkgpio@e8a0b000arm,pl061arm,primecellT蠰 T8HT4~ apb_pclkL`TP901[PMU0_SSI][PMU1_SSI][PMU2_SSI][PMU0_CLKOUT][JTAG_TCK][JTAG_TMS]gpio@e8a0c000arm,pl061arm,primecellT U8HT4~  apb_pclkC`[JTAG_TRST_N][JTAG_TDI][JTAG_TDO]NCNC[I2C3_SCL][I2C3_SDA]NCgpio@e8a0d000arm,pl061arm,primecellT V8HT4~! apb_pclkG`NCNCNCGPIO-JGPIO_020_HDMI_SELGPIO-LGPIO_022_UFSBUCK_INT_NGPIO-Ggpio@e8a0e000arm,pl061arm,primecellT W8HT4~" apb_pclkJ`[CSI0_MCLK][CSI1_MCLK]NC[I2C2_SCL][I2C2_SDA][I2C3_SCL][I2C3_SDA]NCgpio@e8a0f000arm,pl061arm,primecellT X8HT4~# apb_pclkA`NCNCPWR_BTN_NGPIO_035_PMU2_ENGPIO_036_USB_HUB_RESETNCNCNCvgpio@e8a10000arm,pl061arm,primecellT Y8HT4&~$ apb_pclkQ`GPIO-HGPIO_041_HDMI_PDTP904TP905NCNCGPIO_046_HUB_VDD33_ENGPIO_047_PMU1_ENgpio@e8a11000arm,pl061arm,primecellT Z8HT4.~% apb_pclkA`NCNCNCGPIO_051_WIFI_ENGPIO-I[SD_DAT1][SD_DAT2][UART1_RXD]xgpio@e8a12000arm,pl061arm,primecellT  [8HT46~& apb_pclky`[UART1_TXD][UART0_CTS][UART0_RTS][UART0_RXD][UART0_TXD][SOC_BT_UART4_CTS_N][SOC_BT_UART4_RTS_N][SOC_BT_UART4_RXD]gpio@e8a13000arm,pl061arm,primecellT0 \8HT4>~' apb_pclk?`[SOC_BT_UART4_TXD]NC[PMU_HKADC_SSI]NCGPIO_068_SELNCNCNCgpio@e8a14000arm,pl061arm,primecellT@ ]8HT4F~( apb_pclk`NCNCNCGPIO-KNCNCNCNCgpio@e8a15000arm,pl061arm,primecellTP ^8HT4N~) apb_pclk`NCNCNCNCNCNCNCNCgpio@e8a16000arm,pl061arm,primecellT` _8HT4V~* apb_pclk$`NC[PCIE_PERST_N]NCNCNCNCNCNC?gpio@e8a17000arm,pl061arm,primecellTp `8H T4^4e~+ apb_pclk`NCNCNCNCgpio@e8a18000arm,pl061arm,primecellT血 a8HT4f~, apb_pclk`NCNCNCNCNCNCNCNCgpio@e8a19000arm,pl061arm,primecellT衐 b8HT4n~- apb_pclk`NCNCNCNCNCNCNCNCgpio@e8a1a000arm,pl061arm,primecellT衠 c8HT4v~. apb_pclk'`NCNCNCNCNCNCGPIO_126_BT_ENTP902/gpio@e8a1b000arm,pl061arm,primecellT衰 d8H~/ apb_pclk`gpio@e8a1c000arm,pl061arm,primecellT e8H~0 apb_pclk`gpio@ff3b4000arm,pl061arm,primecellT;@ f8HT5~1 apb_pclkm`[UFS_REF_CLK][UFS_RST_N][SPI1_SCLK][SPI1_DIN][SPI1_DOUT][SPI1_CS]GPIO_150_USER_LED1GPIO_151_USER_LED2>gpio@ff3b5000arm,pl061arm,primecellT;P g8HT5~2 apb_pclk`NCNCNCNCgpio@e8a1f000arm,pl061arm,primecellT h8HT6~3 apb_pclk@`[SD_CLK][SD_CMD][SD_DATA0][SD_DATA1][SD_DATA2][SD_DATA3]gpio@e8a20000arm,pl061arm,primecellT i8H~T74 apb_pclk^`[WL_SDIO_CLK][WL_SDIO_CMD][WL_SDIO_DATA0][WL_SDIO_DATA1][WL_SDIO_DATA2][WL_SDIO_DATA3]gpio@fff0b000arm,pl061arm,primecellT j8HT8~9 apb_pclkd`[GPIO_176_PMU_PWR_HOLD]NA[SYSCLK_EN]GPIO_179_WL_WAKEUP_APGPIO_180_HDMI_INTNAGPIO-F[I2C0_SCL]Jgpio@fff0c000arm,pl061arm,primecellT k8HT8~9 apb_pclk^`[I2C0_SDA][I2C1_SCL][I2C1_SDA][I2C1_SCL][I2C1_SDA]GPIO_189_USER_LED3GPIO_190_USER_LED4wgpio@fff0d000arm,pl061arm,primecellT l8HT8 ~9 apb_pclkt`[PCM_DI][PCM_DO][PCM_CLK][PCM_FS][GPIO_196_I2S2_DI][GPIO_197_I2S2_DO][GPIO_198_I2S2_XCLK][GPIO_199_I2S2_XFS]gpio@fff0e000arm,pl061arm,primecellT m8H T88~9 apb_pclkz`NCNCGPIO_202_VBUS_TYPECGPIO_203_SD_DETGPIO_204_PMU12_IRQ_NGPIO_205_WIFI_ACTIVEGPIO_206_USBSW_SELGPIO_207_BT_ACTIVE@gpio@fff0f000arm,pl061arm,primecellT n8HT8~9 apb_pclkL`GPIO-AGPIO-BGPIO-CGPIO-DGPIO-E[PCIE_CLKREQ_N][PCIE_WAKE_N][SPI0_CLK]gpio@fff10000arm,pl061arm,primecellT o8HT8$~9 apb_pclkB`[SPI0_DIN][SPI0_DOUT][SPI0_CS]GPIO_219_CC_INTNCNC[PMU_INT]gpio@fff1d000arm,pl061arm,primecellT 8H~9 apb_pclk`spi@ffd68000arm,pl022arm,primecellTր+ t apb_pclk)default7:;p wAokayHLS-SPI0spi@ff3b3000arm,pl022arm,primecellT;0+ 85 apb_pclk)default7<=p w>AokayHHS-SPI1pcie@f4000000hisilicon,kirin960-pcie@T? dbiapbphyconfig+Hpci~ (msi(RSQP:pcie_phy_refpcie_auxpcie_apb_phypcie_apb_syspcie_aclk ?ufs@ff3b0000#hisilicon,hi3660-ufsjedec,ufs-1.1 T;;  feref_clkphy_clk " rstdwmmc1@ff37f000hisilicon,hi3660-dw-mshcT7+ Kciubiu0 "reset9Aokay.;HUc n@)default 7ABCwDEdwmmc2@ff3ff000hisilicon,hi3660-dw-mshcT?+ Lciubiu "resetAokay)default 7FGHwIwlcore@2 ti,wl1837T Jwatchdog@e8a06000arm,sp805arm,primecellT` ,  wdog_clkapb_pclkwatchdog@e8a07000arm,sp805arm,primecellTp -  wdog_clkapb_pclktsensor@fff30000hisilicon,hi3660-tsensorT Kthermal-zonescls0dKtripstrip-point@0#Opassivetrip-point@1$#OpassiveLcooling-mapsmap0.L30@map1.L30@ usb3_otg_bc@ff200000sysconsimple-mfdT usb-phyhisilicon,hi3660-usb-phyOZsM$fNdwc3@ff100000 snps,dwc3TIrefbus_earlyI C@0"N usb3-phyotg super-speedutmi1Jc}hostport+endpoint@0TOendpoint@1TPetm@ecc40000"arm,coresight-etm4xarm,primecellT apb_pclkDout-portsportendpointQVetm@ecd40000"arm,coresight-etm4xarm,primecellT apb_pclkDout-portsportendpointRWetm@ece40000"arm,coresight-etm4xarm,primecellT apb_pclkDout-portsportendpointSXetm@ecf40000"arm,coresight-etm4xarm,primecellT apb_pclkDout-portsportendpointTYfunnel@ec801000+arm,coresight-dynamic-funnelarm,primecellT apb_pclkout-portsportendpointUZin-ports+port@0TendpointVQport@1TendpointWRport@2TendpointXSport@3TendpointYTetf@ec802000 arm,coresight-tmcarm,primecellT  apb_pclkin-portsportendpointZUout-portsportendpoint[hetm@ed440000"arm,coresight-etm4xarm,primecellTD apb_pclkDout-portsportendpoint\aetm@ed540000"arm,coresight-etm4xarm,primecellTT apb_pclkDout-portsportendpoint]betm@ed640000"arm,coresight-etm4xarm,primecellTd apb_pclkDout-portsportendpoint^cetm@ed740000"arm,coresight-etm4xarm,primecellTt apb_pclkD out-portsportendpoint_dfunnel@ed001000+arm,coresight-dynamic-funnelarm,primecellT apb_pclkout-portsportendpoint`ein-ports+port@0Tendpointa\port@1Tendpointb]port@2Tendpointc^port@3Tendpointd_etf@ed002000 arm,coresight-tmcarm,primecellT  apb_pclkin-portsportendpointe`out-portsportendpointfifunnelarm,coresight-static-funnel apb_pclkout-portsportendpointgkin-ports+port@0Tendpointh[port@1Tendpointiffunnel@ec031000+arm,coresight-dynamic-funnelarm,primecellT apb_pclkout-portsportendpointjlin-ports+port@0Tendpointkgetf@ec036000 arm,coresight-tmcarm,primecellT` apb_pclkin-portsportendpointljout-portsportendpointmnreplicator arm,coresight-static-replicator apb_pclkin-portsportendpointnmout-ports+port@0Tendpointoqport@1Tendpointpretr@ec033000 arm,coresight-tmcarm,primecellT0 apb_pclkin-portsportendpointqotpiu@ec032000!arm,coresight-tpiuarm,primecellT  apb_pclkin-portsportendpointrpgpio-rangespinmux@e896c000pinctrl-singleT * H esst4pmu_pmx_func  csi0_pwd_n_pmx_funcDcsi1_pwd_n_pmx_funcLisp0_pmx_funcXdhisp1_pmx_func\lppwr_key_pmx_functi2c3_pmx_func,0 i2c4_pmx_funcpcie_perstn_pmx_func\usbhub5734_pmx_func uart0_pmx_func$uart1_pmx_func 'uart2_pmx_func )uart3_pmx_func +uart4_pmx_func -uart5_pmx_func 0uart6_pmx_func 2cam0_rst_pmx_funccam1_rst_pmx_func$pinmux@ff37e000pinctrl-singleT7 * Hes6sd_pmx_func0 Apinmux@ff3b6000pinctrl-singleT;`0 * Hes 5ufs_pmx_funcspi3_pmx_func  <pinmux@ff3fd000pinctrl-singleT? * Hes7sdio_pmx_func0 Fpinmux@fff11000pinctrl-singleT * Hes*8i2s2_pmx_func DHLPslimbus_pmx_func,0i2c0_pmx_funci2c1_pmx_func i2c7_pmx_func$("pcie_pmx_funcspi2_pmx_func :i2s0_pmx_func 48<@pinmux@e896c800pinconf-singleT * pmu_cfg_func   i2c3_cfg_func8<!csi0_pwd_n_cfg_funcPcsi1_pwd_n_cfg_funcXisp0_cfg_funcdptisp1_cfg_funchx|pwr_key_cfg_funcuuart1_cfg_func (uart2_cfg_func *uart5_cfg_func 1cam0_rst_cfg_funcuart0_cfg_func%uart6_cfg_func 3uart3_cfg_func ,uart4_cfg_func .cam1_rst_cfg_func0pinmux@ff3b6800pinconf-singleT;h * ufs_cfg_func0spi3_cfg_func   =pinmux@ff3fd800pinconf-singleT? * sdio_clk_cfg_funcGsdio_cfg_func( Hpinmux@ff37e800pinconf-singleT7 * sd_clk_cfg_funcBsd_cfg_func( Cpinmux@fff11800pinconf-singleT * i2c0_cfg_func i2c1_cfg_func$(i2c7_cfg_func,0#slimbus_cfg_func48i2s0_cfg_func @DHLi2s2_cfg_func PTX\pcie_cfg_funcspi2_cfg_func  ;usb_cfg_funcaliases/soc/dwmmc1@ff37f000/soc/dwmmc2@ff3ff000/soc/serial@fdf02000/soc/serial@fdf00000/soc/serial@fdf03000 /soc/serial@ffd74000/soc/serial@fdf01000/soc/serial@fdf05000%/soc/serial@fff32000chosen-serial6:115200n8memory@0HmemoryTreserved-memory+ramoops@32000000ramoopsT29ERreboot-mode-syscon@32100000sysconsimple-mfdT2reboot-modesyscon-reboot-mode^ewfUqwfUwfUkeys gpio-keys)default7tupower v HGPIO Powertleds gpio-ledsuser_led1 Hgreen:user1 > heartbeatuser_led2 Hgreen:user2 >noneuser_led3 Hgreen:user3 wmmc0user_led4 Hgreen:user4 wnonewlan_active_led Hyellow:wlan @phy0txoffbt_active_ledHblue:bt @ hci0-poweroffpmic@fff34000hisilicon,hi6421v530-pmicT@~regulatorsLDO3 VOUT3_1V85w@ ! xLDO9VOUT9_1V8_2V95 2Z ELDO11VOUT11_1V8_2V95 2Z LDO15 VOUT15_3V0 - 7 I xLDO16 VOUT16_2V95 - hDwlan-en-1-8vregulator-fixedwlan-en-regulatorw@ w@ ]x bp sIfirmwareopteelinaro,optee-tz=smc compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpudevice_typeregenable-methodnext-level-cachecpu-idle-statescapacity-dmips-mhzclocksoperating-points-v2#cooling-cellsdynamic-power-coefficientphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-ns#interrupt-cellsinterrupt-controllerinterruptsinterrupt-affinityranges#clock-cells#reset-cellshisi,rst-syscon#mbox-cellsmboxesclock-namesclock-frequencyresetspinctrl-namespinctrl-0statuslabeldata-rolepower-roletry-power-rolesource-pdossink-pdosop-sink-microwattremote-endpointadi,dsi-lanesdma-namesdmasenable-gpiosmax-speed#dma-cellsdma-channelsdma-requestsdma-channel-maskdma-no-ccidma-typeinterrupt-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namesnum-cscs-gpiosreg-namesbus-rangenum-lanesinterrupt-map-maskinterrupt-mapreset-gpiosfreq-table-hzreset-nameshisilicon,peripheral-sysconcard-detect-delaybus-widthcap-sd-highspeedsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104disable-wpcd-gpiosvmmc-supplyvqmmc-supplynon-removablebroken-cdcap-power-off-card#thermal-sensor-cellspolling-delaypolling-delay-passivesustainable-powerthermal-sensorstemperaturehysteresistripcontributioncooling-device#phy-cellshisilicon,pericrg-sysconhisilicon,pctrl-sysconhisilicon,eye-diagram-paramassigned-clocksassigned-clock-ratesphysphy-namesdr_modemaximum-speedphy_typesnps,dis-del-phy-power-chg-quirksnps,lfps_filter_quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirksnps,tx_de_emphasis_quirksnps,tx_de_emphasissnps,dis_enblslpm_quirksnps,gctl-reset-quirkusb-role-switchrole-switch-default-mode#pinctrl-single,gpio-range-cells#pinctrl-cells#gpio-range-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,gpio-rangepinctrl-single,pinspinctrl-single,bias-pulldownpinctrl-single,bias-pulluppinctrl-single,drive-strengthmshc1mshc2serial0serial1serial2serial3serial4serial5serial6stdout-pathrecord-sizeconsole-sizeftrace-sizeoffsetmode-normalmode-bootloadermode-recoverywakeup-sourcelinux,codelinux,default-triggerpanic-indicatordefault-stateregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-boot-onregulator-always-ongpiostartup-delay-usenable-active-high