O8K(2K+hisilicon,hi3670-hikey970hisilicon,hi3670 + 7HiKey970psci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D cpu@0arm,cortex-a53HcpuTXpscifcpu@1arm,cortex-a53HcpuTXpscifcpu@2arm,cortex-a53HcpuTXpscifcpu@3arm,cortex-a53HcpuTXpscifcpu@100arm,cortex-a73HcpuTXpscifcpu@101arm,cortex-a73HcpuTXpscifcpu@102arm,cortex-a73HcpuTXpscifcpu@103arm,cortex-a73HcpuTXpscif interrupt-controller@e82b0000 arm,gic-400@T++ +@ +` n  ftimerarm,armv8-timer 0   Lsoc simple-bus+crg_ctrl@fff35000 hisilicon,hi3670-crgctrlsysconTPf crg_rst_controller.hisilicon,hi3670-resethisilicon,hi3660-reset fpctrl@e8a09000hisilicon,hi3670-pctrlsysconT蠐crg_ctrl@fff34000 hisilicon,hi3670-pmuctrlsysconT@sctrl@fff0a000hisilicon,hi3670-sctrlsysconTfiomcu@ffd7e000hisilicon,hi3670-iomcusysconTmedia1_crgctrl@e87ff000#hisilicon,hi3670-media1-crgsysconTmedia2_crgctrl@e8900000#hisilicon,hi3670-media2-crgsysconTserial@fdf02000arm,pl011arm,primecellT  J uartclkapb_pclkdefault  okay HS-UART0serial@fdf00000arm,pl011arm,primecellT K uartclkapb_pclkdefault  disabledserial@fdf03000arm,pl011arm,primecellT0 L uartclkapb_pclkdefault  okay LS-UART0serial@ffd74000arm,pl011arm,primecellT@ r  uartclkapb_pclkdefault  disabledserial@fdf01000arm,pl011arm,primecellT M uartclkapb_pclkdefault  disabledserial@fdf05000arm,pl011arm,primecellTP N uartclkapb_pclkdefault  disabledserial@fff32000arm,pl011arm,primecellT  O  uartclkapb_pclkdefault okay LS-UART1gpio@e8a0b000arm,pl061arm,primecellT蠰 T( 4n } apb_pclkK@TP901GPIO_003_USB_HUB_RESET_NNC[AP_GPS_REF_CLK][I2C3_SCL][I2C3_SDA]gpio@e8a0c000arm,pl061arm,primecellT U(n ~ apb_pclk[@[UART0_CTS][UART0_RTS][UART0_TXD][UART0_RXD][USER_LED5]GPIO-I[USER_LED3][USER_LED4]gpio@e8a0d000arm,pl061arm,primecellT V(4n  apb_pclk^@GPIO-G[CSI0_MCLK][CSI1_MCLK]GPIO_019_BT_ACTIVE[I2C2_SCL][I2C2_SDA][I2C3_SCL][I2C3_SDA]gpio@e8a0e000arm,pl061arm,primecellT W( 4 n  apb_pclk[@GPIO_024_WIFI_ACTIVEGPIO_025_PERST_M.2[I2C4_SCL][I2C4_SDA]NCGPIO-H[USER_LED1]GPIO-Lgpio@e8a0f000arm,pl061arm,primecellT X(4n  apb_pclkm@GPIO-KGPIO_033_PMU1_ENGPIO_034_USBSW_SEL[SD_DAT1][SD_DAT2][UART1_RXD][UART1_TXD][SOC_GPS_UART3_CTS_N]gpio@e8a10000arm,pl061arm,primecellT Y(4n  apb_pclk@[SOC_GPS_UART3_RTS_N][SOC_GPS_UART3_RXD][SOC_GPS_UART3_TXD][SOC_BT_UART4_CTS_N][SOC_BT_UART4_RTS_N][SOC_BT_UART4_RXD][SOC_BT_UART4_TXD]NCgpio@e8a11000arm,pl061arm,primecellT Z(4"n  apb_pclkd@NCGPIO_049_USER_LED6GPIO_050_CAN_RSTGPIO_051_WIFI_ENGPIO-DGPIO-JGPIO_054_BT_EN[GPIO_055_SEL]f'gpio@e8a12000arm,pl061arm,primecellT  [(4)n  apb_pclk$@[PCIE_PERST_L]NCNCNCNCNCNCNCgpio@e8a13000arm,pl061arm,primecellT0 \(41n  apb_pclk@NCNCNCNCNCNCNCNCgpio@e8a14000arm,pl061arm,primecellT@ ](49n  apb_pclk@NCNCNCNCNCNCNCNCgpio@e8a15000arm,pl061arm,primecellTP ^(4An  apb_pclk@NCNCNCNCNCNCNCNCgpio@e8a16000arm,pl061arm,primecellT` _(4In  apb_pclk@NCNCNCNCNCNCNCNCgpio@e8a17000arm,pl061arm,primecellTp `(4Qn  apb_pclk @NCgpio@e8a18000arm,pl061arm,primecellT血 a(n  apb_pclk@gpio@e8a19000arm,pl061arm,primecellT衐 b(n  apb_pclk@gpio@e8a1a000arm,pl061arm,primecellT衠 c(n  apb_pclk@gpio@e8a1b000arm,pl061arm,primecellT衰 d(4n  apb_pclkm@[WL_SDIO_CLK][WL_SDIO_CMD][WL_SDIO_DATA0][WL_SDIO_DATA1][WL_SDIO_DATA2][WL_SDIO_DATA3][ETH_ISOLATE]NCgpio@e8a1c000arm,pl061arm,primecellT e(4n  apb_pclk@[MINI1CLK_EN]NCgpio@fff28000arm,pl061arm,primecellT f(4*n apb_pclkn@[SPI1_SCLK][SPI1_DIN][SPI1_DOUT][SPI1_CS][POWER_INT_N][CDMA_GPS_SYNC]GPIO_150_PEX_INTAGPIO_151_CAN_INTgpio@fff29000arm,pl061arm,primecellT g(4=n apb_pclk@gpio@e8a1f000arm,pl061arm,primecellT h(4n  apb_pclkd@[SD_CLK][SD_CMD][SD_DATA0][SD_DATA1][SD_DATA2][SD_DATA3]GPIO_166_ETHCLK_ENGPIO_167_USER_LED2gpio@e8a20000arm,pl061arm,primecellT i(4n  apb_pclk*@GPIO_168_GPS_ENGPIO-CGPIO-EGPIO-Bgpio@fff0b000arm,pl061arm,primecellT j(4n apb_pclkg@[PMU_PWR_HOLD]GPIO_177_WL_WAKEUP_AP[JTAG_TCK][JTAG_TMS][JTAG_TDI][JTAG_TMS]GPIO_182_FATAL_ERRNCf%gpio@fff0c000arm,pl061arm,primecellT k(4n apb_pclkm@GPIO_184_JTAG_SELGPIO-F[I2C0_SCL][I2C0_SDA][GPIO_188_I2C1_SCL][GPIO_189_I2C1_SDA][I2C1_SCL][I2C2_SDA]gpio@fff0d000arm,pl061arm,primecellT l(4n apb_pclk<@[SD_LED]NC[PCM_DI][PCM_DO][PCM_CLK][PCM_FS][I2S2_DO]gpio@fff0e000arm,pl061arm,primecellT m(4n apb_pclk@[I2S2_XCLK][I2S2_XFS]GPIO_202_PERST_ETHGPIO_203_PWRON_DETGPIO_204_PMU1_IRQ_NGPIO_205_SD_DETGPIO_206_GPS_MOTION_INTGPIO_207_HDMI_SELfgpio@fff0f000arm,pl061arm,primecellT n(4n apb_pclkG@GPIO-AGPIO_209_VBUS_TYPECNCNCNC[SPI0_SCLK][SPI0_DIN][SPI0_DOUT]gpio@fff10000arm,pl061arm,primecellT o(4n apb_pclk|@[SPI0_CS]GPIO_217_HDMI_PDGPIO_218_GPS_WAKEUP_APGPIO_219_M.2CLK_ENGPIO_220_PERST_MINIGPIO_221_CC_INT[PCIE_CLKREQ_L]NCgpio@fff1d000arm,pl061arm,primecellT (4#n apb_pclki@[PMU0_INT][SPMI_DATA][SPMI_CLK][CAN_SPI_CLK][CAN_SPI_DI][CAN_SPI_DO][CAN_SPI_CS]GPIO_231_HDMI_INTufs@ff3c0000#hisilicon,hi3670-ufsjedec,ufs-2.1 T<>    ref_clkphy_clkP ^ erstdwmmc1@ff37f0002hisilicon,hi3670-dw-mshchisilicon,hi3660-dw-mshcT7+  ciubiu0 ^eresetq okay default  dwmmc2@fc1830002hisilicon,hi3670-dw-mshchisilicon,hi3660-dw-mshcT0+  ciubiu0 ^ereset okay(6@default !"#$wlcore@2 ti,wl1837T %gpio-rangeSf&pinmux@e896c000pinctrl-singleT,t &Rfuart0_pmx_funcTXf uart2_pmx_func  f uart3_pmx_func dhlpfuart4_pmx_func tx|fuart6_pmx_func\`fpinmux@e896c800pinconf-singleT,t uart0_cfg_funcX\6f uart2_cfg_func  6fuart3_cfg_func hlpt6fuart4_cfg_func x|6fuart6_cfg_func`d6fpinmux@fc182000pinctrl-singleT (t & fsdio_pmx_func0 f!pinmux@fc182800pinconf-singleT((t sdio_clk_cfg_func6f"sdio_cfg_func( 6f#pinmux@ff37e000pinctrl-singleT70t & fsd_pmx_func0 fpinmux@ff37e800pinconf-singleT70t sd_clk_cfg_func6fsd_cfg_func( 6fpinmux@fff11000pinctrl-singleT<t &.fpinmux@fff11800pinconf-singleT<t aliasesT/soc/dwmmc1@ff37f000Z/soc/dwmmc2@fc183000`/soc/serial@fdf02000h/soc/serial@fdf00000p/soc/serial@fdf03000x/soc/serial@ffd74000/soc/serial@fdf01000/soc/serial@fdf05000/soc/serial@fff32000chosenserial6:115200n8memory@0HmemoryTregulator-1v8regulator-fixed fixed-1.8Vw@w@f regulator-3v3regulator-fixed fixed-3.3V2Z2Zfwlan-en-1-8vregulator-fixedwlan-en-regulatorw@w@  'pf$ compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpudevice_typeregenable-methodphandle#interrupt-cellsinterruptsinterrupt-controllerclock-frequencyranges#clock-cells#reset-cellshisi,rst-sysconclocksclock-namespinctrl-namespinctrl-0statuslabelgpio-controller#gpio-cellsgpio-rangesgpio-line-namesfreq-table-hzresetsreset-nameshisilicon,peripheral-sysconcard-detect-delaybus-widthsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104cap-sd-highspeeddisable-wpcd-invertedcd-gpiosvmmc-supplyvqmmc-supplynon-removablebroken-cdcap-power-off-card#pinctrl-single,gpio-range-cells#pinctrl-cells#gpio-range-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,gpio-rangepinctrl-single,pinspinctrl-single,bias-pulldownpinctrl-single,bias-pulluppinctrl-single,drive-strengthmshc1mshc2serial0serial1serial2serial3serial4serial5serial6stdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-ongpiostartup-delay-usenable-active-high