80(O(hisilicon,hi6220-hikeyhisilicon,hi6220 +7HiKey Development Boardpsci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D idle-statesHpscicpu-sleeparm,idle-stateUf} cluster-sleeparm,idle-stateUf} cpu@0arm,cortex-a53cpupsci    #27cpu@1arm,cortex-a53cpupsci    #27cpu@2arm,cortex-a53cpupsci    #27cpu@3arm,cortex-a53cpupsci    #27cpu@100arm,cortex-a53cpupsci   #27cpu@101arm,cortex-a53cpupsci   #27cpu@102arm,cortex-a53cpupsci   #27cpu@103arm,cortex-a53cpupsci   #27 l2-cache0cache l2-cache1cachecpu_opp_tableoperating-points-v2L opp00W e^ހl opp01W^ހl opp02W+s@^l opp03W98p^`l opp04WG^KPl interrupt-controller@f6801000 arm,gic-400@ @ ` }  timerarm,armv8-timer 0   soc simple-bus+sram@fff80000!hisilicon,hi6220-sramctrlsyscon ao_ctrl@f7800000hisilicon,hi6220-aoctrlsyscon sys_ctrl@f7030000 hisilicon,hi6220-sysctrlsyscon media_ctrl@f4410000"hisilicon,hi6220-mediactrlsysconATpm_ctrl@f7032000hisilicon,hi6220-pmctrlsyscon acpu_sctrl@f6504000#hisilicon,hi6220-acpu-sctrlsysconP@Xmedianoc_ade@f4520000sysconR@Sstub_clockhisilicon,hi6220-stub-clkmbox-tx  serial@f8015000arm,pl011arm,primecellP $$$uartclkapb_pclkserial@f7111000arm,pl011arm,primecell %uartclkapb_pclkdefault  $rxtx.okay5)Eрbluetooth ti,wl1835-st Z ext_clockserial@f7112000arm,pl011arm,primecell  &uartclkapb_pclkdefault.okay gLS-UART0serial@f7113000arm,pl011arm,primecell0 'uartclkapb_pclkdefault.okay gLS-UART1serial@f7114000arm,pl011arm,primecell@ (uartclkapb_pclkdefault .disableddma@f7370000hisilicon,k3-dma-1.07mx  T  hi6220_dma.okaytimer@f8008000arm,sp804arm,primecelltimer1timer2apb_pclkrtc@f8003000arm,pl031arm,primecell0  % apb_pclkrtc@f8004000arm,pl031arm,primecell@ & apb_pclkpinmux@f7010000pinctrl-single|+ p P X ` h p x       ! + 0 8 J z ~    default!"#$%,gpio-range boot_sel_pmx_func=!emmc_pmx_funcP=  $;sd_pmx_func0=  @sd_pmx_idle0=  Csdio_pmx_func0=(,048<Hsdio_pmx_idle0=(,048<Kisp_pmx_func=$(,048<@DHLPTX\`hkadc_ssi_pmx_func=h"codec_clk_pmx_func=l#codec_pmx_func =ptx|fm_pmx_func =bt_pmx_func =pwm_in_pmx_func=$bl_pwm_pmx_func=%uart0_pmx_func=uart1_pmx_func =uart2_pmx_func =uart3_pmx_func =uart4_pmx_func =uart5_pmx_func=i2c0_pmx_func=0i2c1_pmx_func=2i2c2_pmx_func=4spi0_pmx_func =-pinmux@f7010800pinconf-single+ default&'()*boot_sel_cfg_func=Qnp&hkadc_ssi_cfg_func=lQnp'emmc_clk_cfg_func=Qn p<emmc_cfg_funcH=  $(Qnp=emmc_rst_cfg_func=,Qnp>sd_clk_cfg_func= Qn0pAsd_clk_cfg_idle= QnpDsd_cfg_func(= Qn pBsd_cfg_idle(= QnpEsdio_clk_cfg_func=4Qn pIsdio_clk_cfg_idle=4QnpLsdio_cfg_func(=8<@DHQnpJsdio_cfg_idle(=8<@DHQnpMisp_cfg_func1x=(,048<@DHLPX\`dQnpisp_cfg_idle1=48Qnpisp_cfg_func2=TQnpcodec_clk_cfg_func=pQnp(codec_clk_cfg_idle=pQnpcodec_cfg_func1=tQnpcodec_cfg_func2=x|Qnpcodec_cfg_idle2=x|Qnpfm_cfg_func =Qnpbt_cfg_func =Qnpbt_cfg_idle =Qnppwm_in_cfg_func=Qnp)bl_pwm_cfg_func=Qnp*uart0_cfg_func1=Qnpuart0_cfg_func2=Qnpuart1_cfg_func1=Qnpuart1_cfg_func2=Qnpuart2_cfg_func =Qnpuart3_cfg_func =Qnpuart4_cfg_func =Qnpuart5_cfg_func=Qnpi2c0_cfg_func=Qnp1i2c1_cfg_func=Qnp3i2c2_cfg_func=Qnp5spi0_cfg_func =Qnp.pinmux@f8001800pinconf-singlex+ default+rstout_n_cfg_func=Qnp+pmu_peri_en_cfg_func=Qnpsysclk0_en_cfg_func=Qnpjtag_tdo_cfg_func= Qn prf_reset_cfg_func=ptQnpgpio@f8011000arm,pl061arm,primecell 4} apb_pclkOPWR_HOLDDSI_SELUSB_HUB_RESET_NUSB_SELHDMI_PDWL_REG_ONPWRON_DET5V_HUB_EN6gpio@f8012000arm,pl061arm,primecell  5} apb_pclk:SD_DETHDMI_INTPMU_IRQ_NWL_HOST_WAKENCNCNCBT_REG_ONgpio@f8013000arm,pl061arm,primecell0 6} apb_pclkBGPIO-AGPIO-BGPIO-CGPIO-DGPIO-EUSB_ID_DETUSB_VBUS_DETGPIO-Hgpio@f8014000arm,pl061arm,primecell@ 7,P} apb_pclk%GPIO3_0NCNCNCWLAN_ACTIVENCNC}gpio@f7020000arm,pl061arm,primecell 8,X} apb_pclk?USER_LED1USER_LED2USER_LED3USER_LED4SD_SELNCNCBT_ACTIVE|gpio@f7021000arm,pl061arm,primecell 9,`} apb_pclk?NCNC[UART1_RxD][UART1_TxD][AUX_SSI1]NC[PCM_CLK][PCM_FS]gpio@f7022000arm,pl061arm,primecell  :,h} apb_pclk=[SPI0_DIN][SPI0_DOUT][SPI0_CS][SPI0_SCLK]NCNCNCGPIO-G/gpio@f7023000arm,pl061arm,primecell0 ;,p} apb_pclk$NCNCNCNC[PCM_DI][PCM_DO]NCNCgpio@f7024000arm,pl061arm,primecell@ < ,x,} apb_pclkNC[CEC_CLK_19_2MHZ]NCgpio@f7025000arm,pl061arm,primecellP =,} apb_pclk'GPIO-JGPIO-LNCNCNCNC[ISP_CCLK0]gpio@f7026000arm,pl061arm,primecell` > ,,} apb_pclk?BOOT_SEL[ISP_CCLK1]GPIO-IGPIO-KNCNC[I2C2_SDA][I2C2_SCL]gpio@f7027000arm,pl061arm,primecellp ? ,,} apb_pclk"[I2C3_SDA][I2C3_SCL]NCNCNCgpio@f7028000arm,pl061arm,primecell @ ,!,+} apb_pclk8[BT_PCM_XFS][BT_PCM_DI][BT_PCM_DO]NCNCNCNCGPIO-Fgpio@f7029000arm,pl061arm,primecell A,0} apb_pclkh[UART0_RX][UART0_TX][BT_UART1_CTS][BT_UART1_RTS][BT_UART1_RX][BT_UART1_TX][UART0_CTS][UART0_RTS]gpio@f702a000arm,pl061arm,primecell B,8} apb_pclkZ[UART0_RxD][UART0_TxD][I2C0_SCL][I2C0_SDA][I2C1_SCL][I2C1_SDA][I2C2_SCL][I2C2_SDA]gpio@f702b000arm,pl061arm,primecell C0,J,z,~} apb_pclk NCgpio@f702c000arm,pl061arm,primecell D,} apb_pclkgpio@f702d000arm,pl061arm,primecell E,} apb_pclkgpio@f702e000arm,pl061arm,primecell F,} apb_pclkgpio@f702f000arm,pl061arm,primecell G,} apb_pclkspi@f7106000arm,pl022arm,primecell` 2 apb_pclkdefault-. /.okayi2c@f7100000snps,designware-i2c , ,default01.okayi2c@f7101000snps,designware-i2c -,default23.okayi2c@f7102000snps,designware-i2c  .,default45.okay+adv7533@39 adi,adv75339  6-ports+port@0endpoint>7Wport@2endpoint>8Pusbphyhisilicon,hi6220-usb-phyNY9d:usb@f72c0000hisilicon,hi6220-usb,: usb2-phyotgotg< Mmailbox@f7510000hisilicon,hi6220-mbox Q ^dwmmc0@f723d000hisilicon,hi6220-dw-mshc# Hciubiuresetdefault;<=>?dwmmc1@f723e000hisilicon,hi6220-dw-mshcd# I+ciubiureset defaultidle @AB CDE&8IVcpFG} dwmmc2@f723f000hisilicon,hi6220-dw-mshc# Jciubiureset defaultidle HIJ KLMNO+wlcore@2 ti,wl1835 watchdog@f8005000arm,sp805arm,primecellP  wdog_clkapb_pclktsensor@0,f7030700hisilicon,tsensor  thermal_clkQi2s@f7118000hisilicon,hi6210-i2s { 8dacodeci2s-base$rxtx-portsport@0~endpoint>Pi2s8thermal-zonescls0d Qtripstrip-point@0/;passivetrip-point@1/$;passiveRcooling-mapsmap0FR`K ade@f4100000hisilicon,hi6220-adex Zade_basedST sTTT(clk_ade_coreclk_codec_jpegclk_ade_pix5TTEu**y.okayportendpoint>UVdsi@f4107800hisilicon,hi6220-dsixTpclk.okayports+port@0endpoint>VUport@1endpoint@0>W7debug@f6590000&arm,coresight-cpu-debugarm,primecellY; apb_pclkDdebug@f6592000&arm,coresight-cpu-debugarm,primecellY ; apb_pclkDdebug@f6594000&arm,coresight-cpu-debugarm,primecellY@; apb_pclkDdebug@f6596000&arm,coresight-cpu-debugarm,primecellY`; apb_pclkDdebug@f65d0000&arm,coresight-cpu-debugarm,primecell]; apb_pclkDdebug@f65d2000&arm,coresight-cpu-debugarm,primecell] ; apb_pclkDdebug@f65d4000&arm,coresight-cpu-debugarm,primecell]@; apb_pclkDdebug@f65d6000&arm,coresight-cpu-debugarm,primecell]`; apb_pclkD gpu@f4080000#hisilicon,hi6220-maliarm,mali-450 ~~~~~~~~~~~8gpgpmmupppp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3TT corebus5TTEeDao_g3dmedia_g3dTfunnel@f6401000+arm,coresight-dynamic-funnelarm,primecell@X apb_pclkout-portsportendpoint>Y[in-portsportendpoint>Zbetf@f6402000 arm,coresight-tmcarm,primecell@ X apb_pclkin-portsportendpoint>[Yout-portsportendpoint>\]replicator arm,coresight-static-replicatorX apb_pclkin-portsportendpoint>]\out-ports+port@0endpoint>^`port@1endpoint>_aetr@f6404000 arm,coresight-tmcarm,primecell@@X apb_pclkin-portsportendpoint>`^tpiu@f6405000!arm,coresight-tpiuarm,primecell@PX apb_pclkin-portsportendpoint>a_funnel@f6501000+arm,coresight-dynamic-funnelarm,primecellPX apb_pclkout-portsportendpoint>bZin-ports+port@0endpoint>ckport@1endpoint>dlport@2endpoint>emport@3endpoint>fnport@4endpoint>goport@5endpoint>hpport@6endpoint>iqport@7endpoint>jretm@f659c000"arm,coresight-etm4xarm,primecellYX apb_pclkDsout-portsportendpoint>kcetm@f659d000"arm,coresight-etm4xarm,primecellYX apb_pclkDtout-portsportendpoint>ldetm@f659e000"arm,coresight-etm4xarm,primecellYX apb_pclkDuout-portsportendpoint>meetm@f659f000"arm,coresight-etm4xarm,primecellYX apb_pclkDvout-portsportendpoint>nfetm@f65dc000"arm,coresight-etm4xarm,primecell]X apb_pclkDwout-portsportendpoint>ogetm@f65dd000"arm,coresight-etm4xarm,primecell]X apb_pclkDxout-portsportendpoint>phetm@f65de000"arm,coresight-etm4xarm,primecell]X apb_pclkDyout-portsportendpoint>qietm@f65df000"arm,coresight-etm4xarm,primecell]X apb_pclkD zout-portsportendpoint>rjcti@f6403000 arm,coresight-ctiarm,primecell@0X apb_pclkcti@f6598000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellYX apb_pclkDscti@f6599000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellYX apb_pclkDtcti@f659a000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellYX apb_pclkDucti@f659b000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellYX apb_pclkDvcti@f65d8000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecell]X apb_pclkDwcti@f65d9000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecell]X apb_pclkDxcti@f65da000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecell]X apb_pclkDycti@f65db000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecell]X apb_pclkD zaliases/soc/serial@f8015000/soc/serial@f7111000/soc/serial@f7112000/soc/serial@f7113000chosenserial3:115200n8memory@0memory` `A"reserved-memory+ramoops@21f00000ramoops!linux,cmashared-dma-poolreboot-mode-syscon@5f01000sysconsimple-mfdreboot-modesyscon-reboot-modewfU&wfU6wfUregulator@0regulator-fixedDSYS_5VSLK@kLK@{regulator@1regulator-fixedDVDD_3V3S2Zk2Z{Nregulator@2regulator-fixedD5V_HUBSLK@kLK@ 6{9wl1835-pwrseqmmc-pwrseq-simple 6 ext_clock  Oleds gpio-ledsuser_led1 ggreen:user1 a| heartbeatuser_led2 ggreen:user2 a|mmc0user_led3 ggreen:user3 a|mmc1user_led4 ggreen:user4 a|nonewlan_active_led gyellow:wlan a}phy0txoffbt_active_ledgblue:bt a| hci0-poweroffpmic@f8000000hisilicon,hi655x-pmic} #regulatorsLDO2 DLDO2_2V8S&%k0.xLDO7 DLDO7_SDIOSw@k2Z.xFLDO10 DLDO10_2V85Sw@k-.hGLDO13 DLDO13_1V8Sjk0.xLDO14 DLDO14_2V8S&%k0.xLDO15 DLDO15_1V8Sjk0.xLDO17 DLDO17_2V5S&%k0.xLDO19 DLDO19_3V0Sw@k-.h?LDO21 DLDO21_1V8S-Pk.xLDO22 DLDO22_1V2S kO.xfirmwareopteelinaro,optee-tz=smcsound_cardaudio-graph-cardJ~ compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpuentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usphandlewakeup-latency-usdevice_typeregenable-methodnext-level-cacheclocksoperating-points-v2cpu-idle-states#cooling-cellsdynamic-power-coefficientopp-sharedopp-hzopp-microvoltclock-latency-ns#interrupt-cellsinterrupt-controllerinterruptsranges#clock-cells#reset-cellshisilicon,hi6220-clk-srammbox-namesmboxesclock-namespinctrl-namespinctrl-0dmasdma-namesstatusassigned-clocksassigned-clock-ratesenable-gpioslabel#dma-cellsdma-channelsdma-requestsdma-no-ccidma-type#pinctrl-cells#gpio-range-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,gpio-range#pinctrl-single,gpio-range-cellspinctrl-single,pinspinctrl-single,bias-pulldownpinctrl-single,bias-pulluppinctrl-single,drive-strengthgpio-controller#gpio-cellsgpio-line-namesgpio-rangesbus-idenable-dmanum-cscs-gpiosi2c-sda-hold-time-nspd-gpiosadi,dsi-lanes#sound-dai-cellsremote-endpoint#phy-cellsphy-supplyhisilicon,peripheral-sysconphysphy-namesdr_modeg-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-size#mbox-cellsresetsreset-namescap-mmc-highspeednon-removablebus-widthvmmc-supplypinctrl-1card-detect-delaycap-sd-highspeedsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50vqmmc-supplydisable-wpcd-gpioscap-power-off-cardmmc-pwrseq#thermal-sensor-cellshisilicon,sysctrl-syscondai-formatpolling-delaypolling-delay-passivesustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicereg-nameshisilicon,noc-syscondma-coherentinterrupt-namesarm,cs-dev-assocserial0serial1serial2serial3stdout-pathrecord-sizeconsole-sizeftrace-sizereusablelinux,cma-defaultoffsetmode-normalmode-bootloadermode-recoveryregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-onvin-supplygpioreset-gpiospost-power-on-delay-mspower-off-delay-uslinux,default-triggerpanic-indicatordefault-statepmic-gpiosregulator-enable-ramp-delaydais