r8mH(m$rockchip,rk3308-evbrockchip,rk3308 +7Rockchip RK3308 EVBaliases=/i2c@ff040000B/i2c@ff050000G/i2c@ff060000L/i2c@ff070000Q/serial@ff0a0000Y/serial@ff0b0000a/serial@ff0c0000i/serial@ff0d0000q/serial@ff0e0000y/spi@ff120000~/spi@ff130000/spi@ff140000cpus+cpu@0cpuarm,cortex-a35psciZ cpu@1cpuarm,cortex-a35pscicpu@2cpuarm,cortex-a35psci cpu@3cpuarm,cortex-a35psci idle-statespscicpu-sleeparm,idle-state+<Sxdtl2-cachecachecpu0-opp-tableoperating-points-v2opp-408000000Q ~~r`@opp-600000000#F ~~r`@opp-8160000000, r`@opp-1008000000< **r`@arm-pmuarm,cortex-a35-pmu0STUV external-mac-clock fixed-clock mac_clkinpsci arm,psci-1.0smctimerarm,armv8-timer0   xin24m fixed-clockn6xin24mgrf@ff000000&rockchip,rk3308-grfsysconsimple-mfd?reboot-modesyscon-reboot-modeRB'RB3RB?RBMRB syscon@ff00b000-rockchip,rk3308-detect-grfsysconsimple-mfd+syscon@ff00c000+rockchip,rk3308-core-grfsysconsimple-mfd+i2c@ff040000(rockchip,rk3308-i2crockchip,rk3399-i2c [i2cpclk  gdefaultu + disabledi2c@ff050000(rockchip,rk3308-i2crockchip,rk3399-i2c [i2cpclk  gdefaultu + disabledi2c@ff060000(rockchip,rk3308-i2crockchip,rk3399-i2c [i2cpclk  gdefaultu + disabledi2c@ff070000(rockchip,rk3308-i2crockchip,rk3399-i2c [i2cpclk gdefaultu+ disabledwatchdog@ff080000 snps,dw-wdt   disabledserial@ff0a0000&rockchip,rk3308-uartsnps,dw-apb-uart  [baudclkapb_pclkgdefault u disabledserial@ff0b0000&rockchip,rk3308-uartsnps,dw-apb-uart  [baudclkapb_pclkgdefault u disabledserial@ff0c0000&rockchip,rk3308-uartsnps,dw-apb-uart  [baudclkapb_pclkgdefaultu disabledserial@ff0d0000&rockchip,rk3308-uartsnps,dw-apb-uart  [baudclkapb_pclkgdefaultu disabledserial@ff0e0000&rockchip,rk3308-uartsnps,dw-apb-uart [baudclkapb_pclkgdefaultuokayspi@ff120000(rockchip,rk3308-spirockchip,rk3066-spi +[spiclkapb_pclktxrxgdefaultu disabledspi@ff130000(rockchip,rk3308-spirockchip,rk3066-spi +[spiclkapb_pclktxrxgdefaultu  disabledspi@ff140000(rockchip,rk3308-spirockchip,rk3066-spi +[spiclkapb_pclk!!txrxgdefaultu"#$% disabledpwm@ff160000(rockchip,rk3308-pwmrockchip,rk3328-pwmy [pwmpclkgdefaultu& disabledpwm@ff160010(rockchip,rk3308-pwmrockchip,rk3328-pwmy [pwmpclkgdefaultu' disabledpwm@ff160020(rockchip,rk3308-pwmrockchip,rk3328-pwm y [pwmpclkgdefaultu( disabledpwm@ff160030(rockchip,rk3308-pwmrockchip,rk3328-pwm0y [pwmpclkgdefaultu) disabledpwm@ff170000(rockchip,rk3308-pwmrockchip,rk3328-pwmx [pwmpclkgdefaultu* disabledpwm@ff170010(rockchip,rk3308-pwmrockchip,rk3328-pwmx [pwmpclkgdefaultu+ disabledpwm@ff170020(rockchip,rk3308-pwmrockchip,rk3328-pwm x [pwmpclkgdefaultu, disabledpwm@ff170030(rockchip,rk3308-pwmrockchip,rk3328-pwm0x [pwmpclkgdefaultu- disabledpwm@ff180000(rockchip,rk3308-pwmrockchip,rk3328-pwm [pwmpclkgdefaultu.okayRpwm@ff180010(rockchip,rk3308-pwmrockchip,rk3328-pwm [pwmpclkgdefaultu/ disabledpwm@ff180020(rockchip,rk3308-pwmrockchip,rk3328-pwm  [pwmpclkgdefaultu0 disabledpwm@ff180030(rockchip,rk3308-pwmrockchip,rk3328-pwm0 [pwmpclkgdefaultu1 disabledrktimer@ff1a0000rockchip,rk3288-timer   [pclktimersaradc@ff1e0000.rockchip,rk3308-saradcrockchip,rk3399-saradc %%[saradcapb_pclkF saradc-apbokay2Kbus simple-bus+dma-controller@ff2c0000arm,pl330arm,primecell,@ [apb_pclkdma-controller@ff2d0000arm,pl330arm,primecell-@ [apb_pclk!i2s@ff350000(rockchip,rk3308-i2srockchip,rk3066-i2s5 4\[i2s_clki2s_hclk!! txrxreset-mreset-hgdefaultu3456 disabledi2s@ff360000(rockchip,rk3308-i2srockchip,rk3066-i2s6 5^[i2s_clki2s_hclk! rxreset-mreset-h disabledspdif-tx@ff3a0000,rockchip,rk3308-spdifrockchip,rk3066-spdif: 7b [mclkhclk! txgdefaultu7 disabledmmc@ff4800000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcH@ L 012[biuciuciu-driveciu-sample&рgdefaultu89:; disabledmmc@ff4900000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcI@ M :;<[biuciuciu-driveciu-sample&р disabledmmc@ff4a00000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcJ@ N 567[biuciuciu-driveciu-sample&рgdefault u<=> disabledclock-controller@ff500000rockchip,rk3308-cruP4A?N^interrupt-controller@ff580000 arm,gic-400@XX X@ X`   ssram@fff80000 mmio-sram+ddr-sram@0vad-sram@8000pinctrlrockchip,rk3308-pinctrlA?+gdefaultu@gpio0@ff220000rockchip,gpio-bank" (sMgpio1@ff230000rockchip,gpio-bank# )sgpio2@ff240000rockchip,gpio-bank$ *sgpio3@ff250000rockchip,gpio-bank% +sgpio4@ff260000rockchip,gpio-bank& ,spcfg-pull-upJpcfg-pull-downGpcfg-pull-noneCpcfg-pull-none-2mapcfg-pull-up-2mapcfg-pull-up-4maIpcfg-pull-none-4maHpcfg-pull-down-4mapcfg-pull-none-8maApcfg-pull-up-8maBpcfg-pull-none-12ma Epcfg-pull-up-12ma Dpcfg-pull-none-smtFpcfg-output-highpcfg-output-lowpcfg-input-highpcfg-inputemmcemmc-clk& Aemmc-cmd&Bemmc-pwren& Cemmc-rstn& Cemmc-bus1&Bemmc-bus4@&BBBBemmc-bus8&BBBBBBBBflashflash-csn0& Cflash-rdy& Cflash-ale& Cflash-cle& Cflash-wrn&Cflash-rdn& Cflash-bus8&DDDDDDDDgmacrmii-pins&EEECCCCC Cmac-refclk-12ma& Emac-refclk& Cgmac-m1rmiim1-pins&EEECCCCC Cmacm1-refclk-12ma& Emacm1-refclk& Ci2c0i2c0-xfer &FF i2c1i2c1-xfer & F F i2c2i2c2-xfer &FF i2c3-m0i2c3m0-xfer &FFi2c3-m1i2c3m1-xfer & F Fi2c3-m2i2c3m2-xfer &FFi2s_2ch_0i2s-2ch-0-mclk& Ci2s-2ch-0-sclk& C3i2s-2ch-0-lrck&C4i2s-2ch-0-sdo&C6i2s-2ch-0-sdi&C5i2s_8ch_0i2s-8ch-0-mclk&Ci2s-8ch-0-sclktx&Ci2s-8ch-0-sclkrx&Ci2s-8ch-0-lrcktx&Ci2s-8ch-0-lrckrx&Ci2s-8ch-0-sdo0& Ci2s-8ch-0-sdo1& Ci2s-8ch-0-sdo2& Ci2s-8ch-0-sdo3& Ci2s-8ch-0-sdi0& Ci2s-8ch-0-sdi1&Ci2s-8ch-0-sdi2&Ci2s-8ch-0-sdi3&Ci2s_8ch_1_m0i2s-8ch-1-m0-mclk&Ci2s-8ch-1-m0-sclktx&Ci2s-8ch-1-m0-sclkrx&Ci2s-8ch-1-m0-lrcktx&Ci2s-8ch-1-m0-lrckrx&Ci2s-8ch-1-m0-sdo0&Ci2s-8ch-1-m0-sdo1-sdi3&Ci2s-8ch-1-m0-sdo2-sdi2& Ci2s-8ch-1-m0-sdo3_sdi1& Ci2s-8ch-1-m0-sdi0& Ci2s_8ch_1_m1i2s-8ch-1-m1-mclk& Ci2s-8ch-1-m1-sclktx& Ci2s-8ch-1-m1-sclkrx&Ci2s-8ch-1-m1-lrcktx&Ci2s-8ch-1-m1-lrckrx&Ci2s-8ch-1-m1-sdo0&Ci2s-8ch-1-m1-sdo1-sdi3&Ci2s-8ch-1-m1-sdo2-sdi2&Ci2s-8ch-1-m1-sdo3_sdi1&Ci2s-8ch-1-m1-sdi0&Cpdm_m0pdm-m0-clk&Cpdm-m0-sdi0& Cpdm-m0-sdi1& Cpdm-m0-sdi2& Cpdm-m0-sdi3&Cpdm_m1pdm-m1-clk&Cpdm-m1-sdi0&Cpdm-m1-sdi1&Cpdm-m1-sdi2&Cpdm-m1-sdi3&Cpdm_m2pdm-m2-clkm&Cpdm-m2-clk&Cpdm-m2-sdi0& Cpdm-m2-sdi1&Cpdm-m2-sdi2&Cpdm-m2-sdi3&Cpwm0pwm0-pin& Cpwm0-pin-pull-down& G.pwm1pwm1-pin&C/pwm1-pin-pull-down&Gpwm2pwm2-pin&C0pwm2-pin-pull-down&Gpwm3pwm3-pin&C1pwm3-pin-pull-down&Gpwm4pwm4-pin&C*pwm4-pin-pull-down&Gpwm5pwm5-pin&C+pwm5-pin-pull-down&Gpwm6pwm6-pin&C,pwm6-pin-pull-down&Gpwm7pwm7-pin&C-pwm7-pin-pull-down&Gpwm8pwm8-pin& C&pwm8-pin-pull-down& Gpwm9pwm9-pin& C'pwm9-pin-pull-down& Gpwm10pwm10-pin& C(pwm10-pin-pull-down& Gpwm11pwm11-pin&C)pwm11-pin-pull-down&Grtcrtc-32k&C@sdmmcsdmmc-clk&H8sdmmc-cmd&I9sdmmc-det&I:sdmmc-pwren&Hsdmmc-bus1&Isdmmc-bus4@&IIII;sdiosdio-clk&A>sdio-cmd&B=sdio-pwren&Asdio-wrpt&Asdio-intn&Asdio-bus1&Bsdio-bus4@&BBBB<spdif_inspdif-in&Cspdif_outspdif-out&C7spi0spi0-clk&Ispi0-csn0&Ispi0-miso&Ispi0-mosi&Ispi1spi1-clk& Ispi1-csn0& Ispi1-miso& Ispi1-mosi& I spi1-m1spi1m1-miso&Ispi1m1-mosi&Ispi1m1-clk&Ispi1m1-csn0& Ispi2spi2-clk&I"spi2-csn0&I#spi2-miso&I$spi2-mosi&I%tsadctsadc-otp-pin& Ctsadc-otp-out& Cuart0uart0-xfer &JJuart0-cts&Cuart0-rts&Cuart0-rts-pin&Cuart1uart1-xfer &JJuart1-cts&Cuart1-rts&Cuart2-m0uart2m0-xfer &JJuart2-m1uart2m1-xfer &JJuart3uart3-xfer & J Juart3-m1uart3m1-xfer &JJuart4uart4-xfer & JJuart4-cts&Cuart4-rts&Cuart4-rts-pin&Cbuttonspwr-key&JLusbusb-drv&CQsdio-pwrseqwifi-enable-h&Cchosen4serial4:1500000n8adc-keys0 adc-keys@KLbuttons]dkw@func-key functionFPadc-keys1 adc-keys@KLbuttons]dkw@esc-keymicmute>home-keyumode menu-keyplay vol-down-keyr volume downvol-up-keys volume upFPgpio-keys gpio-keysgdefaultuLpower MtGPIO Key Powerdvcc12v-dcinregulator-fixed vcc12v_dcin 4Nvcc5v0-sysregulator-fixed vcc5v0_sysLK@LK@ 4FNPvcc-1v8regulator-fixedvcc_1v8w@w@ 4FO2vcc-ddrregulator-fixedvcc_ddr`` 4FPvcc-ioregulator-fixedvcc_io2Z2Z 4FPOvccio-flashregulator-fixed vccio_flash2Z2Z 4FOvcc5v0-hostregulator-fixed QMVgdefaultuQ vbus_hostFPvdd-corepwm-regulatoriR vdd_core xr` 4nPvdd-logregulator-fixedvdd_log 4FPvdd-1v0regulator-fixedvdd_1v0B@B@ 4FP compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4spi0spi1spi2device_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-idle-statesnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsoffsetmode-bootloadermode-loadermode-normalmode-recoverymode-fastbootclock-namespinctrl-namespinctrl-0statusreg-shiftreg-io-widthdmasdma-names#pwm-cells#io-channel-cellsresetsreset-namesvref-supplyrangesarm,pl330-periph-burst#dma-cellsbus-widthfifo-depthmax-frequency#reset-cellsrockchip,grfassigned-clocksassigned-clock-rates#interrupt-cellsinterrupt-controllergpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathio-channelsio-channel-namespoll-intervalkeyup-threshold-microvoltlinux,codelabelpress-threshold-microvoltautorepeatgpiosdebounce-intervalwakeup-sourceregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onvin-supplygpioenable-active-highpwmsregulator-settling-time-up-uspwm-supply