p8k(j&firefly,roc-rk3308-ccrockchip,rk3308 +7Firefly ROC-RK3308-CC boardaliases=/i2c@ff040000B/i2c@ff050000G/i2c@ff060000L/i2c@ff070000Q/serial@ff0a0000Y/serial@ff0b0000a/serial@ff0c0000i/serial@ff0d0000q/serial@ff0e0000y/spi@ff120000~/spi@ff130000/spi@ff140000cpus+cpu@0cpuarm,cortex-a35psciZ cpu@1cpuarm,cortex-a35pscicpu@2cpuarm,cortex-a35psci cpu@3cpuarm,cortex-a35psci idle-statespscicpu-sleeparm,idle-state+<Sxdtl2-cachecachecpu0-opp-tableoperating-points-v2opp-408000000Q ~~r`@opp-600000000#F ~~r`@opp-8160000000, r`@opp-1008000000< **r`@arm-pmuarm,cortex-a35-pmu0STUV external-mac-clock fixed-clock mac_clkinpsci arm,psci-1.0smctimerarm,armv8-timer0   xin24m fixed-clockn6xin24mgrf@ff000000&rockchip,rk3308-grfsysconsimple-mfdBreboot-modesyscon-reboot-modeRB'RB3RB?RBMRB syscon@ff00b000-rockchip,rk3308-detect-grfsysconsimple-mfd+syscon@ff00c000+rockchip,rk3308-core-grfsysconsimple-mfd+i2c@ff040000(rockchip,rk3308-i2crockchip,rk3399-i2c [i2cpclk  gdefaultu + disabledi2c@ff050000(rockchip,rk3308-i2crockchip,rk3399-i2c [i2cpclk  gdefaultu +okayrtc@51 nxp,pcf8563Qi2c@ff060000(rockchip,rk3308-i2crockchip,rk3399-i2c [i2cpclk  gdefaultu + disabledi2c@ff070000(rockchip,rk3308-i2crockchip,rk3399-i2c [i2cpclk gdefaultu+ disabledwatchdog@ff080000 snps,dw-wdt   disabledserial@ff0a0000&rockchip,rk3308-uartsnps,dw-apb-uart  [baudclkapb_pclkgdefault u disabledserial@ff0b0000&rockchip,rk3308-uartsnps,dw-apb-uart  [baudclkapb_pclkgdefault u disabledserial@ff0c0000&rockchip,rk3308-uartsnps,dw-apb-uart  [baudclkapb_pclkgdefaultuokayserial@ff0d0000&rockchip,rk3308-uartsnps,dw-apb-uart  [baudclkapb_pclkgdefaultu disabledserial@ff0e0000&rockchip,rk3308-uartsnps,dw-apb-uart [baudclkapb_pclkgdefault u disabledspi@ff120000(rockchip,rk3308-spirockchip,rk3066-spi +[spiclkapb_pclktxrxgdefaultu disabledspi@ff130000(rockchip,rk3308-spirockchip,rk3066-spi +[spiclkapb_pclktxrxgdefaultu !" disabledspi@ff140000(rockchip,rk3308-spirockchip,rk3066-spi +[spiclkapb_pclk##txrxgdefaultu$%&' disabledpwm@ff160000(rockchip,rk3308-pwmrockchip,rk3328-pwmy [pwmpclkgdefaultu( disabledpwm@ff160010(rockchip,rk3308-pwmrockchip,rk3328-pwmy [pwmpclkgdefaultu) disabledpwm@ff160020(rockchip,rk3308-pwmrockchip,rk3328-pwm y [pwmpclkgdefaultu* disabledpwm@ff160030(rockchip,rk3308-pwmrockchip,rk3328-pwm0y [pwmpclkgdefaultu+ disabledpwm@ff170000(rockchip,rk3308-pwmrockchip,rk3328-pwmx [pwmpclkgdefaultu, disabledpwm@ff170010(rockchip,rk3308-pwmrockchip,rk3328-pwmx [pwmpclkgactiveu-okayPpwm@ff170020(rockchip,rk3308-pwmrockchip,rk3328-pwm x [pwmpclkgdefaultu. disabledpwm@ff170030(rockchip,rk3308-pwmrockchip,rk3328-pwm0x [pwmpclkgdefaultu/ disabledpwm@ff180000(rockchip,rk3308-pwmrockchip,rk3328-pwm [pwmpclkgdefaultu0okayUpwm@ff180010(rockchip,rk3308-pwmrockchip,rk3328-pwm [pwmpclkgdefaultu1 disabledpwm@ff180020(rockchip,rk3308-pwmrockchip,rk3328-pwm  [pwmpclkgdefaultu2 disabledpwm@ff180030(rockchip,rk3308-pwmrockchip,rk3328-pwm0 [pwmpclkgdefaultu3 disabledrktimer@ff1a0000rockchip,rk3288-timer   [pclktimersaradc@ff1e0000.rockchip,rk3308-saradcrockchip,rk3399-saradc %%[saradcapb_pclkF saradc-apb disabledbus simple-bus+dma-controller@ff2c0000arm,pl330arm,primecell,@ [apb_pclkdma-controller@ff2d0000arm,pl330arm,primecell-@ [apb_pclk#i2s@ff350000(rockchip,rk3308-i2srockchip,rk3066-i2s5 4\[i2s_clki2s_hclk## txrxreset-mreset-hgdefaultu4567 disabledi2s@ff360000(rockchip,rk3308-i2srockchip,rk3066-i2s6 5^[i2s_clki2s_hclk# rxreset-mreset-h disabledspdif-tx@ff3a0000,rockchip,rk3308-spdifrockchip,rk3066-spdif: 7b [mclkhclk# txgdefaultu8 disabledmmc@ff4800000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcH@ L 012[biuciuciu-driveciu-sampleрgdefaultu9:;<okay(:K,]jw=>mmc@ff4900000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcI@ M :;<[biuciuciu-driveciu-sampleрokay(mmc@ff4a00000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcJ@ N 567[biuciuciu-driveciu-sampleрgdefault u?@A disabledclock-controller@ff500000rockchip,rk3308-cruPBinterrupt-controller@ff580000 arm,gic-400@XX X@ X`    sram@fff80000 mmio-sram+ddr-sram@0vad-sram@8000pinctrlrockchip,rk3308-pinctrlB+gdefaultuCgpio0@ff220000rockchip,gpio-bank" ( 0 Ngpio1@ff230000rockchip,gpio-bank# ) 0 gpio2@ff240000rockchip,gpio-bank$ * 0 gpio3@ff250000rockchip,gpio-bank% + 0 gpio4@ff260000rockchip,gpio-bank& , 0 Spcfg-pull-up<Mpcfg-pull-downIJpcfg-pull-noneXFpcfg-pull-none-2maXepcfg-pull-up-2ma<epcfg-pull-up-4ma<eLpcfg-pull-none-4maXeKpcfg-pull-down-4maIepcfg-pull-none-8maXeDpcfg-pull-up-8ma<eEpcfg-pull-none-12maXe Hpcfg-pull-up-12ma<e Gpcfg-pull-none-smtXtIpcfg-output-highpcfg-output-lowpcfg-input-high<pcfg-inputemmcemmc-clk Demmc-cmdEemmc-pwren Femmc-rstn Femmc-bus1Eemmc-bus4@EEEEemmc-bus8EEEEEEEEflashflash-csn0 Fflash-rdy Fflash-ale Fflash-cle Fflash-wrnFflash-rdn Fflash-bus8GGGGGGGGgmacrmii-pinsHHHFFFFF Fmac-refclk-12ma Hmac-refclk Fgmac-m1rmiim1-pinsHHHFFFFF Fmacm1-refclk-12ma Hmacm1-refclk Fi2c0i2c0-xfer II i2c1i2c1-xfer  I I i2c2i2c2-xfer II i2c3-m0i2c3m0-xfer IIi2c3-m1i2c3m1-xfer  I Ii2c3-m2i2c3m2-xfer IIi2s_2ch_0i2s-2ch-0-mclk Fi2s-2ch-0-sclk F4i2s-2ch-0-lrckF5i2s-2ch-0-sdoF7i2s-2ch-0-sdiF6i2s_8ch_0i2s-8ch-0-mclkFi2s-8ch-0-sclktxFi2s-8ch-0-sclkrxFi2s-8ch-0-lrcktxFi2s-8ch-0-lrckrxFi2s-8ch-0-sdo0 Fi2s-8ch-0-sdo1 Fi2s-8ch-0-sdo2 Fi2s-8ch-0-sdo3 Fi2s-8ch-0-sdi0 Fi2s-8ch-0-sdi1Fi2s-8ch-0-sdi2Fi2s-8ch-0-sdi3Fi2s_8ch_1_m0i2s-8ch-1-m0-mclkFi2s-8ch-1-m0-sclktxFi2s-8ch-1-m0-sclkrxFi2s-8ch-1-m0-lrcktxFi2s-8ch-1-m0-lrckrxFi2s-8ch-1-m0-sdo0Fi2s-8ch-1-m0-sdo1-sdi3Fi2s-8ch-1-m0-sdo2-sdi2 Fi2s-8ch-1-m0-sdo3_sdi1 Fi2s-8ch-1-m0-sdi0 Fi2s_8ch_1_m1i2s-8ch-1-m1-mclk Fi2s-8ch-1-m1-sclktx Fi2s-8ch-1-m1-sclkrxFi2s-8ch-1-m1-lrcktxFi2s-8ch-1-m1-lrckrxFi2s-8ch-1-m1-sdo0Fi2s-8ch-1-m1-sdo1-sdi3Fi2s-8ch-1-m1-sdo2-sdi2Fi2s-8ch-1-m1-sdo3_sdi1Fi2s-8ch-1-m1-sdi0Fpdm_m0pdm-m0-clkFpdm-m0-sdi0 Fpdm-m0-sdi1 Fpdm-m0-sdi2 Fpdm-m0-sdi3Fpdm_m1pdm-m1-clkFpdm-m1-sdi0Fpdm-m1-sdi1Fpdm-m1-sdi2Fpdm-m1-sdi3Fpdm_m2pdm-m2-clkmFpdm-m2-clkFpdm-m2-sdi0 Fpdm-m2-sdi1Fpdm-m2-sdi2Fpdm-m2-sdi3Fpwm0pwm0-pin Fpwm0-pin-pull-down J0pwm1pwm1-pinF1pwm1-pin-pull-downJpwm2pwm2-pinF2pwm2-pin-pull-downJpwm3pwm3-pinF3pwm3-pin-pull-downJpwm4pwm4-pinF,pwm4-pin-pull-downJpwm5pwm5-pinFpwm5-pin-pull-downJ-pwm6pwm6-pinF.pwm6-pin-pull-downJpwm7pwm7-pinF/pwm7-pin-pull-downJpwm8pwm8-pin F(pwm8-pin-pull-down Jpwm9pwm9-pin F)pwm9-pin-pull-down Jpwm10pwm10-pin F*pwm10-pin-pull-down Jpwm11pwm11-pinF+pwm11-pin-pull-downJrtcrtc-32kFCsdmmcsdmmc-clkK9sdmmc-cmdL:sdmmc-detL;sdmmc-pwrenKsdmmc-bus1Lsdmmc-bus4@LLLL<sdiosdio-clkDAsdio-cmdE@sdio-pwrenDsdio-wrptDsdio-intnDsdio-bus1Esdio-bus4@EEEE?spdif_inspdif-inFspdif_outspdif-outF8spi0spi0-clkLspi0-csn0Lspi0-misoLspi0-mosiLspi1spi1-clk Lspi1-csn0 L spi1-miso L!spi1-mosi L"spi1-m1spi1m1-misoLspi1m1-mosiLspi1m1-clkLspi1m1-csn0 Lspi2spi2-clkL$spi2-csn0L%spi2-misoL&spi2-mosiL'tsadctsadc-otp-pin Ftsadc-otp-out Fuart0uart0-xfer MMuart0-ctsFuart0-rtsFuart0-rts-pinFuart1uart1-xfer MMuart1-ctsFuart1-rtsFuart2-m0uart2m0-xfer MMuart2-m1uart2m1-xfer MMuart3uart3-xfer  M Muart3-m1uart3m1-xfer MMuart4uart4-xfer  MMuart4-ctsFuart4-rtsFuart4-rts-pinFir-receiverir-recv-pinFObuttonspwr-keyMchosenserial2:1500000n8ir-receivergpio-ir-receiver NgdefaultuOir_tx pwm-ir-txPaleds gpio-ledsled-0firefly:red:powerir-power-clickon Nled-1firefly:blue:userir-user-clickoff N typec-vcc5vregulator-fixed typec_vcc5v LK@#LK@;OQvcc5v0-sysregulator-fixed vcc5v0_sys LK@#LK@;OaQRvcc-ioregulator-fixedvcc_io 2Z#2Z;OaRTvcc-sdmmcregulator-gpio vcc_sdmmc w@#2Z Nw@2ZaR>vcc-sdregulator-fixed lSvcc_sd 2Z#2Z;OaT=vdd-corepwm-regulatorU vdd_core x#r`q|;ORvdd-logregulator-fixedvdd_log #;OaR compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4spi0spi1spi2device_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-idle-statesnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsoffsetmode-bootloadermode-loadermode-normalmode-recoverymode-fastbootclock-namespinctrl-namespinctrl-0statusreg-shiftreg-io-widthdmasdma-names#pwm-cells#io-channel-cellsresetsreset-namesrangesarm,pl330-periph-burst#dma-cellsbus-widthfifo-depthmax-frequencycap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-hs200-1_8vnon-removable#reset-cellsrockchip,grfassigned-clocksassigned-clock-rates#interrupt-cellsinterrupt-controllergpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathgpiospwmslabellinux,default-triggerdefault-stateregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onvin-supplygpioregulator-init-microvoltregulator-settling-time-up-uspwm-supply