g8}(}T$rockchip,rk3328-evbrockchip,rk3328 +7Rockchip RK3328 EVBaliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000cpus+cpu@0}cpuarm,cortex-a53xpsci cpu@1}cpuarm,cortex-a53xpsci cpu@2}cpuarm,cortex-a53xpsci cpu@3}cpuarm,cortex-a53xpsci idle-statespscicpu-sleeparm,idle-state 1HxYi l2-cache0cache opp_table0operating-points-v2z opp-408000000Q~@opp-600000000#F~@opp-8160000000,B@@opp-1008000000<@opp-1200000000G(@opp-1296000000M?d @bus simple-bus+dmac@ff1f0000arm,pl330arm,primecell@ apb_pclk analog-soundsimple-audio-cardi2s*Analog Adisabledsimple-audio-card,cpuHsimple-audio-card,codecHarm-pmuarm,cortex-a53-pmu0defgR display-subsystemrockchip,display-subsysteme hdmi-soundsimple-audio-cardi2s*HDMI Adisabledsimple-audio-card,cpuHsimple-audio-card,codecHpsciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0   xin24m fixed-clockkxn6xin24m Ai2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s )7i2s_clki2s_hclk  txrx Adisabled i2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s *8i2s_clki2s_hclktxrx Adisabled i2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s +9i2s_clki2s_hclktxrx Adisabledspdif@ff030000rockchip,rk3328-spdif .: mclkhclk txdefault Adisabledpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclkrxdefaultsleep Adisabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd 7io-domains"rockchip,rk3328-io-voltage-domain Adisabledgrf-gpiorockchip,rk3328-grf-gpiopower-controller!rockchip,rk3328-power-controller+ 9power-domain@6power-domain@5power-domain@8Freboot-modesyscon-reboot-mode RB RB.RB >RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 7&baudclkapb_pclktxrxdefault JW Adisabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 8'baudclkapb_pclktxrxdefault  !JW Adisabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 9(baudclkapb_pclktxrxdefault"JWAokayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c $+7 i2cpclkdefault# Adisabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c %+8 i2cpclkdefault$Aokaypmic@18rockchip,rk805 %kxin32krk805-clkout2default&a''''((regulatorsDCDC_REG1 vdd_logic 4 +regulator-state-mem=UB@DCDC_REG2vdd_arm 4 + regulator-state-mem=U~DCDC_REG3vcc_ddr+regulator-state-mem=DCDC_REG4vcc_io2Z2Z+ (regulator-state-mem=U2ZLDO_REG1vcc_18w@w@+regulator-state-mem=Uw@LDO_REG2 vcc18_emmcw@w@+regulator-state-mem=Uw@LDO_REG3vdd_10B@B@+regulator-state-mem=UB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c &+9 i2cpclkdefault) Adisabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c '+: i2cpclkdefault* Adisabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 1+ spiclkapb_pclk txrxdefault+,-. Adisabledwatchdog@ff1a0000 snps,dw-wdt (pwm@ff1b0000rockchip,rk3328-pwm< pwmpclkdefault/q Adisabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclkdefault0q Adisabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclkdefault1q Adisabledpwm@ff1b0030rockchip,rk3328-pwm0 2< pwmpclkdefault2q Adisabledthermal-zonessoc-thermal|3tripstrip-point0ppassivetrip-point1Lpassive 4soc-crits criticalcooling-mapsmap040 tsadc@ff250000rockchip,rk3328-tsadc% :$ P$tsadcapb_pclkinitdefaultsleep565)B 0tsadc-apb<7I`Aokay 3efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efusev id@7cpu-leakage@17logic-leakage@19cpu-version@1a Badc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( P%saradcapb_pclk)V 0saradc-apb Adisabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1 buscore)fiommu@ff330200rockchip,iommu3 ` h265e_mmu aclkiface Adisablediommu@ff340800rockchip,iommu4@ b vepu_mmuF aclkiface Adisabledvideo-codec@ff350000rockchip,rk3328-vpu5  vdpuF aclkhclk89iommu@ff350800rockchip,iommu5@  vpu_mmuF aclkiface9 8iommu@ff360480rockchip,iommu 6@6@ J rkvdec_mmuB aclkiface Adisabledvop@ff370000rockchip,rk3328-vop7>  x;aclk_vopdclk_vophclk_vop) 0axiahbdclk: Adisabledport+ endpoint@0; @iommu@ff373f00rockchip,iommu7?  vop_mmu; aclkiface Adisabled :hdmi@ff3c0000rockchip,rk3328-dw-hdmi<J#GFiahbisfrcec<hdmidefault =>?<7 Adisabled portsportendpoint@ ;codec@ff410000rockchip,rk3328-codecA* pclkmclk<7 Adisabled phy@ff430000rockchip,rk3328-hdmi-phyC SAysysclkrefoclkrefpclk hdmi_phykB cpu-version Adisabled <clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD<7kx=&'(ABDC"\5H4$'zAAA| n6n6n6n6#FLGрxhxhрxhxh syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2-phy@100rockchip,rk3328-usb2phyAphyclk usb480m_phyk{'CAokay Cotg-port$;<=otg-bvalidotg-idlinestateAokay Thost-port > linestateAokay Ummc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@   =!JNbiuciuciu-driveciu-sample>IрAokayWasdefaultDEFGHmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@   >"KObiuciuciu-driveciu-sample>IрAokayWsIdefault JKLmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@  ?#LPbiuciuciu-driveciu-sample>IрAokayWadefault MNOethernet@ff540000rockchip,rk3328-gmacT macirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac)c 0stmmaceth<7 Adisabledethernet@ff550000rockchip,rk3328-gmacU<7 macirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy)bd0stmmacethmac-phyrmiiPoutputAokayQe'Tmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22V)ddefaultRS" Pusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X Motg4otg<N]@ T usb2-phyAokayusb@ff5c0000 generic-ehci\  NCUusbAokayusb@ff5d0000 generic-ohci]  NCUusbAokayusb@ff600000rockchip,rk3328-dwc3snps,dwc3` C`aref_clksuspend_clkbus_clk4otg lutmi_wideu  Adisabledinterrupt-controller@ff811000 arm,gic-400#4@ @ `    pinctrlrockchip,rk3328-pinctrl<7+gpio0@ff210000rockchip,gpio-bank! 34# cgpio1@ff220000rockchip,gpio-bank" 44# bgpio2@ff230000rockchip,gpio-bank# 54# %gpio3@ff240000rockchip,gpio-bank$ 64#pcfg-pull-upI Xpcfg-pull-downV `pcfg-pull-nonee Vpcfg-pull-none-2maer _pcfg-pull-up-2maIrpcfg-pull-up-4maIr Ypcfg-pull-none-4maer \pcfg-pull-down-4maVrpcfg-pull-none-8maer Zpcfg-pull-up-8maIr [pcfg-pull-none-12maer  ]pcfg-pull-up-12maIr  ^pcfg-output-highpcfg-output-lowpcfg-input-highI Wpcfg-inputi2c0i2c0-xfer VV #i2c1i2c1-xfer VV $i2c2i2c2-xfer  VV )i2c3i2c3-xfer VV *i2c3-pins VVhdmi_i2chdmii2c-xfer VV >pdm-0pdmm0-clkV pdmm0-fsyncVpdmm0-sdi0V pdmm0-sdi1V pdmm0-sdi2V pdmm0-sdi3V pdmm0-clk-sleepW pdmm0-sdi0-sleepW pdmm0-sdi1-sleepW pdmm0-sdi2-sleepW pdmm0-sdi3-sleepW pdmm0-fsync-sleepWtsadcotp-pin V 5otp-out V 6uart0uart0-xfer  VX uart0-cts V uart0-rts V uart0-rts-pin Vuart1uart1-xfer VX uart1-ctsV uart1-rtsV !uart1-rts-pinVuart2-0uart2m0-xfer VXuart2-1uart2m1-xfer VX "spi0-0spi0m0-clkXspi0m0-cs0 Xspi0m0-tx Xspi0m0-rx Xspi0m0-cs1 Xspi0-1spi0m1-clkXspi0m1-cs0Xspi0m1-txXspi0m1-rxXspi0m1-cs1Xspi0-2spi0m2-clkX +spi0m2-cs0X .spi0m2-txX ,spi0m2-rxX -i2s1i2s1-mclkVi2s1-sclkVi2s1-lrckrxVi2s1-lrcktxVi2s1-sdiVi2s1-sdoVi2s1-sdio1Vi2s1-sdio2Vi2s1-sdio3Vi2s1-sleepWWWWWWWWWi2s2-0i2s2m0-mclkVi2s2m0-sclkVi2s2m0-lrckrxVi2s2m0-lrcktxVi2s2m0-sdiVi2s2m0-sdoVi2s2m0-sleep`WWWWWWi2s2-1i2s2m1-mclkVi2s2m1-sclkVi2sm1-lrckrxVi2s2m1-lrcktxVi2s2m1-sdiVi2s2m1-sdoVi2s2m1-sleepPWWWWWspdif-0spdifm0-txVspdif-1spdifm1-txVspdif-2spdifm2-txV sdmmc0-0sdmmc0m0-pwrenYsdmmc0m0-pinYsdmmc0-1sdmmc0m1-pwrenYsdmmc0m1-pinY dsdmmc0sdmmc0-clkZ Dsdmmc0-cmd[ Esdmmc0-dectnY Fsdmmc0-wrprtYsdmmc0-bus1[sdmmc0-bus4@[[[[ Gsdmmc0-pinsYYYYYYYYsdmmc0extsdmmc0ext-clk\sdmmc0ext-cmdYsdmmc0ext-wrprtYsdmmc0ext-dectnYsdmmc0ext-bus1Ysdmmc0ext-bus4@YYYYsdmmc0ext-pinsYYYYYYYYsdmmc1sdmmc1-clk Z Lsdmmc1-cmd [ Ksdmmc1-pwren[sdmmc1-wrprt[sdmmc1-dectn[sdmmc1-bus1[sdmmc1-bus4@[[[[ Jsdmmc1-pins Y YYYYYYYYemmcemmc-clk] Memmc-cmd^ Nemmc-pwrenVemmc-rstnoutVemmc-bus1^emmc-bus4@^^^^emmc-bus8^^^^^^^^ Opwm0pwm0-pinV /pwm1pwm1-pinV 0pwm2pwm2-pinV 1pwmirpwmir-pinV 2gmac-1rgmiim1-pins` Z \\Z\\\ \ \Z Z\\ZZZ Z\ZZZZrmiim1-pins_]____ _ _] ] V VVVVVgmac2phyfephyled-speed10Vfephyled-duplexVfephyled-rxm1V Rfephyled-txm1Vfephyled-linkm1V Stsadc_pintsadc-int Vtsadc-pin Vhdmi_pinhdmi-cecV =hdmi-hpd` ?cif-0dvp-d2d9-m0VVVVV V V VVVVVcif-1dvp-d2d9-m1VVVVVVVVVVVVpmicpmic-int-lX &sdio-pwrseqwifi-enable-hV achosenserial2:1500000n8dc-12vregulator-fixeddc_12v+ esdio-pwrseqmmc-pwrseq-simpledefaulta b Isdmmc-regulatorregulator-fixed cdefaultdvcc_sd2Z2Z( Hvcc-sysregulator-fixedvcc_sys+LK@LK@e 'vcc-phy-regulatorregulator-fixedvcc_phy+ Q compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterruptsarm,pl330-periph-burstclock-names#dma-cellssimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1gpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesnps,txpblphy-modephy-handleclock_in_outphy-supplyassigned-clock-ratephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathreset-gpiosgpiovin-supply