8x( @'friendlyarm,nanopi-r2srockchip,rk3328 +7FriendlyElec NanoPi R2Saliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000cpus+cpu@0}cpuarm,cortex-a53xpsci cpu@1}cpuarm,cortex-a53xpsci cpu@2}cpuarm,cortex-a53xpsci cpu@3}cpuarm,cortex-a53xpsci idle-statespscicpu-sleeparm,idle-state 1HxYi l2-cache0cache opp_table0operating-points-v2z opp-408000000Q~@opp-600000000#F~@opp-8160000000,B@@opp-1008000000<@opp-1200000000G(@opp-1296000000M?d @bus simple-bus+dmac@ff1f0000arm,pl330arm,primecell@ apb_pclk analog-soundsimple-audio-cardi2s*Analog Adisabledsimple-audio-card,cpuHsimple-audio-card,codecHarm-pmuarm,cortex-a53-pmu0defgR display-subsystemrockchip,display-subsysteme  Adisabledhdmi-soundsimple-audio-cardi2s*HDMI Adisabledsimple-audio-card,cpuHsimple-audio-card,codecHpsciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0   xin24m fixed-clockkxn6xin24m Di2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s )7i2s_clki2s_hclk  txrx Adisabled i2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s *8i2s_clki2s_hclktxrx Adisabled i2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s +9i2s_clki2s_hclktxrx Adisabledspdif@ff030000rockchip,rk3328-spdif .: mclkhclk txdefault Adisabledpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclkrxdefaultsleep Adisabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd :io-domains"rockchip,rk3328-io-voltage-domainAokay"0grf-gpiorockchip,rk3328-grf-gpio>Npower-controller!rockchip,rk3328-power-controllerZ+ <power-domain@6power-domain@5power-domain@8Freboot-modesyscon-reboot-modenuRBRBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 7&baudclkapb_pclktxrxdefault  !" Adisabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 8'baudclkapb_pclktxrxdefault #$% Adisabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 9(baudclkapb_pclktxrxdefault&Aokayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c $+7 i2cpclkdefault' Adisabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c %+8 i2cpclkdefault(Aokaypmic@18rockchip,rk805 )kxin32krk805-clkout2>N*default++ ++!-+regulatorsDCDC_REG19vdd_logH\n 4 0regulator-state-memB@DCDC_REG29vdd_armH\n 4 0 regulator-state-mem~DCDC_REG39vcc_ddrH\regulator-state-memDCDC_REG4 9vcc_io_33H\n2Z2Z regulator-state-mem2ZLDO_REG19vcc_18H\nw@w@ regulator-state-memw@LDO_REG2 9vcc18_emmcH\nw@w@ regulator-state-memw@LDO_REG39vdd_10H\nB@B@regulator-state-memB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c &+9 i2cpclkdefault, Adisabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c '+: i2cpclkdefault- Adisabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 1+ spiclkapb_pclk txrxdefault./01 Adisabledwatchdog@ff1a0000 snps,dw-wdt (pwm@ff1b0000rockchip,rk3328-pwm< pwmpclkdefault2 Adisabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclkdefault3 Adisabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclkdefault4Aokaypwm@ff1b0030rockchip,rk3328-pwm0 2< pwmpclkdefault5 Adisabledthermal-zonessoc-thermal(6tripstrip-point08pDpassivetrip-point18LDpassive 7soc-crit8sD criticalcooling-mapsmap0O70T ctsadc@ff250000rockchip,rk3328-tsadc% :p$P$tsadcapb_pclkinitdefaultsleep898B tsadc-apb:Aokay 6efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efuse id@7cpu-leakage@17logic-leakage@19cpu-version@1a2 Eadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( P7%saradcapb_pclkV saradc-apb Adisabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TZW]XY[\"Igpgpmmupppp0ppmmu0pp1ppmmu1 buscorefiommu@ff330200rockchip,iommu3 ` Ih265e_mmu aclkifaceY Adisablediommu@ff340800rockchip,iommu4@ b Ivepu_mmuF aclkifaceY Adisabledvideo-codec@ff350000rockchip,rk3328-vpu5  IvdpuF aclkhclkf;m<iommu@ff350800rockchip,iommu5@  Ivpu_mmuF aclkifaceYm< ;iommu@ff360480rockchip,iommu 6@6@ J Irkvdec_mmuB aclkifaceY Adisabledvop@ff370000rockchip,rk3328-vop7>  x;aclk_vopdclk_vophclk_vop axiahbdclkf= Adisabledport+ endpoint@0{> Ciommu@ff373f00rockchip,iommu7?  Ivop_mmu; aclkifaceY Adisabled =hdmi@ff3c0000rockchip,rk3328-dw-hdmi<#GFiahbisfrcec?hdmidefault @AB: Adisabled portsportendpoint{C >codec@ff410000rockchip,rk3328-codecA* pclkmclk: Adisabled phy@ff430000rockchip,rk3328-hdmi-phyC SDysysclkrefoclkrefpclk hdmi_phykE cpu-version Adisabled ?clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD:kpx=&'(ABDC"\5H4$zDDD|n6n6n6n6#FLGрxhxhрxhxh syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2-phy@100rockchip,rk3328-usb2phyDphyclk usb480m_phykp{FAokay Fotg-port$;<=Iotg-bvalidotg-idlinestateAokay Shost-port > IlinestateAokay Tmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@   =!JNbiuciuciu-driveciu-sampleрAokay GHIJdefault%2?LZKfmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@   >"KObiuciuciu-driveciu-sampleр Adisabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@  ?#LPbiuciuciu-driveciu-sampleр Adisabledethernet@ff540000rockchip,rk3328-gmacT Imacirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc stmmaceth:sAokaypdfLL~inputMrgmiiNdefault$mdiosnps,dwmac-mdio+ethernet-phy@1Odefault'P ) Methernet@ff550000rockchip,rk3328-gmacU: Imacirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphybdstmmacethmac-phyrmiiPs~output Adisabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22VddefaultQR Pusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X Motghost .@ S usb2-phyAokayusb@ff5c0000 generic-ehci\  NFTusbAokayusb@ff5d0000 generic-ohci]  NFTusbAokayusb@ff600000rockchip,rk3328-dwc3snps,dwc3` C`aref_clksuspend_clkbus_clkotg =utmi_wideFg Adisabledinterrupt-controller@ff811000 arm,gic-400 @ @ `    pinctrlrockchip,rk3328-pinctrl:+gpio0@ff210000rockchip,gpio-bank! 3>N  agpio1@ff220000rockchip,gpio-bank" 4>N  )gpio2@ff230000rockchip,gpio-bank# 5>N  egpio3@ff240000rockchip,gpio-bank$ 6>N pcfg-pull-up  Wpcfg-pull-down ' _pcfg-pull-none 6 Upcfg-pull-none-2ma 6 C ^pcfg-pull-up-2ma  Cpcfg-pull-up-4ma  C Xpcfg-pull-none-4ma 6 C [pcfg-pull-down-4ma ' Cpcfg-pull-none-8ma 6 C Ypcfg-pull-up-8ma  C Zpcfg-pull-none-12ma 6 C  \pcfg-pull-up-12ma  C  ]pcfg-output-high Rpcfg-output-low ^pcfg-input-high  i Vpcfg-input ii2c0i2c0-xfer vUU 'i2c1i2c1-xfer vUU (i2c2i2c2-xfer v UU ,i2c3i2c3-xfer vUU -i2c3-pins vUUhdmi_i2chdmii2c-xfer vUU Apdm-0pdmm0-clk vU pdmm0-fsync vUpdmm0-sdi0 vU pdmm0-sdi1 vU pdmm0-sdi2 vU pdmm0-sdi3 vU pdmm0-clk-sleep vV pdmm0-sdi0-sleep vV pdmm0-sdi1-sleep vV pdmm0-sdi2-sleep vV pdmm0-sdi3-sleep vV pdmm0-fsync-sleep vVtsadcotp-pin v U 8otp-out v U 9uart0uart0-xfer v UW uart0-cts v U !uart0-rts v U "uart0-rts-pin v Uuart1uart1-xfer vUW #uart1-cts vU $uart1-rts vU %uart1-rts-pin vUuart2-0uart2m0-xfer vUWuart2-1uart2m1-xfer vUW &spi0-0spi0m0-clk vWspi0m0-cs0 v Wspi0m0-tx v Wspi0m0-rx v Wspi0m0-cs1 v Wspi0-1spi0m1-clk vWspi0m1-cs0 vWspi0m1-tx vWspi0m1-rx vWspi0m1-cs1 vWspi0-2spi0m2-clk vW .spi0m2-cs0 vW 1spi0m2-tx vW /spi0m2-rx vW 0i2s1i2s1-mclk vUi2s1-sclk vUi2s1-lrckrx vUi2s1-lrcktx vUi2s1-sdi vUi2s1-sdo vUi2s1-sdio1 vUi2s1-sdio2 vUi2s1-sdio3 vUi2s1-sleep vVVVVVVVVVi2s2-0i2s2m0-mclk vUi2s2m0-sclk vUi2s2m0-lrckrx vUi2s2m0-lrcktx vUi2s2m0-sdi vUi2s2m0-sdo vUi2s2m0-sleep` vVVVVVVi2s2-1i2s2m1-mclk vUi2s2m1-sclk vUi2sm1-lrckrx vUi2s2m1-lrcktx vUi2s2m1-sdi vUi2s2m1-sdo vUi2s2m1-sleepP vVVVVVspdif-0spdifm0-tx vUspdif-1spdifm1-tx vUspdif-2spdifm2-tx vU sdmmc0-0sdmmc0m0-pwren vXsdmmc0m0-pin vXsdmmc0-1sdmmc0m1-pwren vXsdmmc0m1-pin vX gsdmmc0sdmmc0-clk vY Gsdmmc0-cmd vZ Hsdmmc0-dectn vX Isdmmc0-wrprt vXsdmmc0-bus1 vZsdmmc0-bus4@ vZZZZ Jsdmmc0-pins vXXXXXXXXsdmmc0extsdmmc0ext-clk v[sdmmc0ext-cmd vXsdmmc0ext-wrprt vXsdmmc0ext-dectn vXsdmmc0ext-bus1 vXsdmmc0ext-bus4@ vXXXXsdmmc0ext-pins vXXXXXXXXsdmmc1sdmmc1-clk v Ysdmmc1-cmd v Zsdmmc1-pwren vZsdmmc1-wrprt vZsdmmc1-dectn vZsdmmc1-bus1 vZsdmmc1-bus4@ vZZZZsdmmc1-pins v X XXXXXXXXemmcemmc-clk v\emmc-cmd v]emmc-pwren vUemmc-rstnout vUemmc-bus1 v]emmc-bus4@ v]]]]emmc-bus8 v]]]]]]]]pwm0pwm0-pin vU 2pwm1pwm1-pin vU 3pwm2pwm2-pin vU 4pwmirpwmir-pin vU 5gmac-1rgmiim1-pins` v Y [[Y[[[ [ [Y Y[[YYY Y[YYYY Nrmiim1-pins v^\^^^^ ^ ^\ \ U UUUUUgmac2phyfephyled-speed10 vUfephyled-duplex vUfephyled-rxm1 vU Qfephyled-txm1 vUfephyled-linkm1 vU Rtsadc_pintsadc-int v Utsadc-pin v Uhdmi_pinhdmi-cec vU @hdmi-hpd v_ Bcif-0dvp-d2d9-m0 vUUUUU U U UUUUUcif-1dvp-d2d9-m1 vUUUUUUUUUUUUbuttonreset-button-pin vU `ethernet-phyeth-phy-reset-pin v_ Oledslan-led-pin vU bsys-led-pin vU cwan-led-pin vU dpmicpmic-int-l vW *sdsdio-vcc-pin vW fchosen serial2:1500000n8gmac-clock fixed-clockxsY@ gmac_clkink Lkeys gpio-keys`defaultreset reset a  2leds gpio-leds bcddefaultled-0 e nanopi-r2s:green:lanled-1 a nanopi-r2s:red:sysled-2 e nanopi-r2s:green:wansdmmcio-regulatorregulator-gpio  )fdefault 9vcc_io_sdioHnw@2Z  voltage w@2Z  sdmmc-regulatorregulator-fixed agdefault9vcc_sd\n2Z2Z  Kvdd-5vregulator-fixed9vdd_5vH\nLK@LK@ + compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterruptsarm,pl330-periph-burstclock-names#dma-cellssimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplysnps,txpblclock_in_outphy-handlephy-modephy-supplyrx_delaysnps,aaltx_delayreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathlabellinux,codedebounce-intervalenable-active-highregulator-settling-time-usregulator-typestartup-delay-usvin-supplygpio