8( ppine64,rock64rockchip,rk3328 +7Pine64 Rock64aliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000cpus+cpu@0}cpuarm,cortex-a53xpsci cpu@1}cpuarm,cortex-a53xpsci cpu@2}cpuarm,cortex-a53xpsci cpu@3}cpuarm,cortex-a53xpsci idle-statespscicpu-sleeparm,idle-state 1HxYi l2-cache0cache opp_table0operating-points-v2z opp-408000000Q~@opp-600000000#F~@opp-8160000000,B@@opp-1008000000<@opp-1200000000G(@opp-1296000000M?d @bus simple-bus+dmac@ff1f0000arm,pl330arm,primecell@ apb_pclk analog-soundsimple-audio-cardi2s*Analog Adisabledsimple-audio-card,cpuHsimple-audio-card,codecHarm-pmuarm,cortex-a53-pmu0defgR display-subsystemrockchip,display-subsysteme hdmi-soundsimple-audio-cardi2s*HDMI Adisabledsimple-audio-card,cpuHsimple-audio-card,codecHpsciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0   xin24m fixed-clockkxn6xin24m Gi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s )7i2s_clki2s_hclk  txrx Adisabled i2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s *8i2s_clki2s_hclktxrxAokay port jendpointi2s" Fi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s +9i2s_clki2s_hclktxrx Adisabledspdif@ff030000rockchip,rk3328-spdif .: mclkhclk txdefaultAokayport kendpoint lpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclkrxdefaultsleep Adisabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd ;io-domains"rockchip,rk3328-io-voltage-domainAokay" 0>Lgrf-gpiorockchip,rk3328-grf-gpioYi Epower-controller!rockchip,rk3328-power-controlleru+ =power-domain@6power-domain@5power-domain@8Freboot-modesyscon-reboot-modeRBRBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 7&baudclkapb_pclktxrxdefault !"# Adisabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 8'baudclkapb_pclktxrxdefault $%& Adisabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 9(baudclkapb_pclktxrxdefault'Aokayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c $+7 i2cpclkdefault( Adisabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c %+8 i2cpclkdefault)Aokaypmic@18rockchip,rk805 *kxin32krk805-clkout2Yidefault+ ,,$,0,<H, iregulatorsDCDC_REG1 Tvdd_logicc 4{ 0regulator-state-memB@DCDC_REG2Tvdd_armc 4{ 0 regulator-state-mem~DCDC_REG3Tvcc_ddrregulator-state-memDCDC_REG4Tvcc_ioc2Z{2Z regulator-state-mem2ZLDO_REG1Tvcc_18cw@{w@ regulator-state-memw@LDO_REG2 Tvcc18_emmccw@{w@ regulator-state-memw@LDO_REG3Tvdd_10cB@{B@regulator-state-memB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c &+9 i2cpclkdefault- Adisabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c '+: i2cpclkdefault. Adisabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 1+ spiclkapb_pclk txrxdefault/012Aokayspiflash@0jedec,spi-norwatchdog@ff1a0000 snps,dw-wdt (pwm@ff1b0000rockchip,rk3328-pwm< pwmpclkdefault3 Adisabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclkdefault4 Adisabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclkdefault5 Adisabledpwm@ff1b0030rockchip,rk3328-pwm0 2< pwmpclkdefault6 Adisabledthermal-zonessoc-thermal5CU7tripstrip-point0epqpassivetrip-point1eLqpassive 8soc-critesq criticalcooling-mapsmap0|80 tsadc@ff250000rockchip,rk3328-tsadc% :$P$tsadcapb_pclkinitdefaultsleep9:9B tsadc-apb;Aokay0 7efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efuseK id@7cpu-leakage@17logic-leakage@19cpu-version@1a_ Hadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( Pd%saradcapb_pclkV saradc-apb Adisabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TZW]XY[\"vgpgpmmupppp0ppmmu0pp1ppmmu1 buscorefiommu@ff330200rockchip,iommu3 ` vh265e_mmu aclkiface Adisablediommu@ff340800rockchip,iommu4@ b vvepu_mmuF aclkiface Adisabledvideo-codec@ff350000rockchip,rk3328-vpu5  vvdpuF aclkhclk<=iommu@ff350800rockchip,iommu5@  vvpu_mmuF aclkiface= <iommu@ff360480rockchip,iommu 6@6@ J vrkvdec_mmuB aclkiface Adisabledvop@ff370000rockchip,rk3328-vop7>  x;aclk_vopdclk_vophclk_vop axiahbdclk>Aokayport+ endpoint@0? Diommu@ff373f00rockchip,iommu7?  vvop_mmu; aclkifaceAokay >hdmi@ff3c0000rockchip,rk3328-dw-hdmi<#GFiahbisfrcec@hdmidefault ABC;Aokay portsportendpointD ?codec@ff410000rockchip,rk3328-codecA* pclkmclk;Aokay E port@0endpointF phy@ff430000rockchip,rk3328-hdmi-phyC SGysysclkrefoclkrefpclk hdmi_phykH cpu-versionAokay @clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD;kx=&'(ABDC"\5H4$zGGG|n6n6n6n6#FLGрxhxhрxhxh syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2-phy@100rockchip,rk3328-usb2phyGphyclk usb480m_phyk{IAokay Iotg-port$;<=votg-bvalidotg-idlinestateAokay Xhost-port > vlinestateAokay Ymmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@   =!JNbiuciuciu-driveciu-sampleрAokay#5FdefaultJKLMQNmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@   >"KObiuciuciu-driveciu-sampleр Adisabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@  ?#LPbiuciuciu-driveciu-sampleрAokay#]ldefault OPQQzethernet@ff540000rockchip,rk3328-gmacT vmacirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc stmmaceth;AokaydfRRinputrgmiidefaultS T 'P $ethernet@ff550000rockchip,rk3328-gmacU; vmacirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphybdstmmacethmac-phyrmiiUoutput Adisabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22VddefaultVW& Uusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X Motg8host@Ra@ X usb2-phyAokayusb@ff5c0000 generic-ehci\  NIYusbAokayusb@ff5d0000 generic-ohci]  NIYusbAokayusb@ff600000rockchip,rk3328-dwc3snps,dwc3` C`aref_clksuspend_clkbus_clk8host putmi_widey Aokayinterrupt-controller@ff811000 arm,gic-400 ' 8@ @ `    pinctrlrockchip,rk3328-pinctrl;+gpio0@ff210000rockchip,gpio-bank! 3Yi 8 ' egpio1@ff220000rockchip,gpio-bank" 4Yi 8 ' Tgpio2@ff230000rockchip,gpio-bank# 5Yi 8 ' *gpio3@ff240000rockchip,gpio-bank$ 6Yi 8 'pcfg-pull-up M \pcfg-pull-down Z dpcfg-pull-none i Zpcfg-pull-none-2ma i v cpcfg-pull-up-2ma M vpcfg-pull-up-4ma M v ]pcfg-pull-none-4ma i v `pcfg-pull-down-4ma Z vpcfg-pull-none-8ma i v ^pcfg-pull-up-8ma M v _pcfg-pull-none-12ma i v  apcfg-pull-up-12ma M v  bpcfg-output-high pcfg-output-low pcfg-input-high M  [pcfg-input i2c0i2c0-xfer ZZ (i2c1i2c1-xfer ZZ )i2c2i2c2-xfer  ZZ -i2c3i2c3-xfer ZZ .i2c3-pins ZZhdmi_i2chdmii2c-xfer ZZ Bpdm-0pdmm0-clk Z pdmm0-fsync Zpdmm0-sdi0 Z pdmm0-sdi1 Z pdmm0-sdi2 Z pdmm0-sdi3 Z pdmm0-clk-sleep [ pdmm0-sdi0-sleep [ pdmm0-sdi1-sleep [ pdmm0-sdi2-sleep [ pdmm0-sdi3-sleep [ pdmm0-fsync-sleep [tsadcotp-pin  Z 9otp-out  Z :uart0uart0-xfer  Z\ !uart0-cts  Z "uart0-rts  Z #uart0-rts-pin  Zuart1uart1-xfer Z\ $uart1-cts Z %uart1-rts Z &uart1-rts-pin Zuart2-0uart2m0-xfer Z\uart2-1uart2m1-xfer Z\ 'spi0-0spi0m0-clk \spi0m0-cs0  \spi0m0-tx  \spi0m0-rx  \spi0m0-cs1  \spi0-1spi0m1-clk \spi0m1-cs0 \spi0m1-tx \spi0m1-rx \spi0m1-cs1 \spi0-2spi0m2-clk \ /spi0m2-cs0 \ 2spi0m2-tx \ 0spi0m2-rx \ 1i2s1i2s1-mclk Zi2s1-sclk Zi2s1-lrckrx Zi2s1-lrcktx Zi2s1-sdi Zi2s1-sdo Zi2s1-sdio1 Zi2s1-sdio2 Zi2s1-sdio3 Zi2s1-sleep [[[[[[[[[i2s2-0i2s2m0-mclk Zi2s2m0-sclk Zi2s2m0-lrckrx Zi2s2m0-lrcktx Zi2s2m0-sdi Zi2s2m0-sdo Zi2s2m0-sleep` [[[[[[i2s2-1i2s2m1-mclk Zi2s2m1-sclk Zi2sm1-lrckrx Zi2s2m1-lrcktx Zi2s2m1-sdi Zi2s2m1-sdo Zi2s2m1-sleepP [[[[[spdif-0spdifm0-tx Z spdif-1spdifm1-tx Zspdif-2spdifm2-tx Zsdmmc0-0sdmmc0m0-pwren ]sdmmc0m0-pin ]sdmmc0-1sdmmc0m1-pwren ]sdmmc0m1-pin ] fsdmmc0sdmmc0-clk ^ Jsdmmc0-cmd _ Ksdmmc0-dectn ] Lsdmmc0-wrprt ]sdmmc0-bus1 _sdmmc0-bus4@ ____ Msdmmc0-pins ]]]]]]]]sdmmc0extsdmmc0ext-clk `sdmmc0ext-cmd ]sdmmc0ext-wrprt ]sdmmc0ext-dectn ]sdmmc0ext-bus1 ]sdmmc0ext-bus4@ ]]]]sdmmc0ext-pins ]]]]]]]]sdmmc1sdmmc1-clk  ^sdmmc1-cmd  _sdmmc1-pwren _sdmmc1-wrprt _sdmmc1-dectn _sdmmc1-bus1 _sdmmc1-bus4@ ____sdmmc1-pins  ] ]]]]]]]]emmcemmc-clk a Oemmc-cmd b Pemmc-pwren Zemmc-rstnout Zemmc-bus1 bemmc-bus4@ bbbbemmc-bus8 bbbbbbbb Qpwm0pwm0-pin Z 3pwm1pwm1-pin Z 4pwm2pwm2-pin Z 5pwmirpwmir-pin Z 6gmac-1rgmiim1-pins`  ^ ``^``` ` `^ ^``^^^ ^`^^^^ Srmiim1-pins cacccc c ca a Z ZZZZZgmac2phyfephyled-speed10 Zfephyled-duplex Zfephyled-rxm1 Z Vfephyled-txm1 Zfephyled-linkm1 Z Wtsadc_pintsadc-int  Ztsadc-pin  Zhdmi_pinhdmi-cec Z Ahdmi-hpd d Ccif-0dvp-d2d9-m0 ZZZZZ Z Z ZZZZZcif-1dvp-d2d9-m1 ZZZZZZZZZZZZirir-int Z hpmicpmic-int-l \ +usb2usb20-host-drv Z gchosen serial2:1500000n8external-gmac-clock fixed-clockxsY@ gmac_clkink Rsdmmc-regulatorregulator-fixed edefaultfTvcc_sdc2Z{2Z  Nvcc-host-5v-regulatorregulator-fixed edefaultg Tvcc_host_5v ,vcc-host1-5v-regulatorregulator-fixed edefaultg Tvcc_host1_5v ,vcc-sysregulator-fixedTvcc_syscLK@{LK@ ,ir-receivergpio-ir-receiver *hdefaultleds gpio-ledsled-0 i mmc0led-1 i heartbeatsoundaudio-graph-card rockchip,rk3328 jkspdif-ditlinux,spdif-ditportendpointl  compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterruptsarm,pl330-periph-burstclock-names#dma-cellssimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesdmasdma-names#sound-dai-cellsdai-formatremote-endpointpinctrl-namespinctrl-0pinctrl-1vccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplypmuio-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltspi-max-frequency#pwm-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsphysphy-namesmute-gpiosnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplymmc-hs200-1_8vnon-removablevqmmc-supplysnps,txpblclock_in_outphy-supplyphy-modesnps,force_thresh_dma_modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphy-handlephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathvin-supplylinux,default-triggerlabeldais