Ð þíM8G°(UGxSolidRun Clearfog Pro A1d!solidrun,clearfog-pro-a1solidrun,clearfog-a1marvell,armada388marvell,armada385marvell,armada380aliases,/soc/internal-regs/gpio@181002/soc/internal-regs/gpio@18140 8/soc/internal-regs/serial@12000 @/soc/internal-regs/serial@12100"H/soc/internal-regs/ethernet@70000"R/soc/internal-regs/ethernet@30000"\/soc/internal-regs/ethernet@34000pmu!arm,cortex-a9-pmufsoc"!marvell,armada380-mbussimple-busz…–à¨èP¹ðñÿð ñ ñ ñ bootrom!marvell,bootrom À devbus-bootcs!marvell,mvebu-devbus Àð¹/ÿÿÿÿÄ Ëdisableddevbus-cs0!marvell,mvebu-devbus Àð¹>ÿÿÿÿÄ Ëdisableddevbus-cs1!marvell,mvebu-devbus Àð¹=ÿÿÿÿÄ Ëdisableddevbus-cs2!marvell,mvebu-devbus Àð¹;ÿÿÿÿÄ Ëdisableddevbus-cs3!marvell,mvebu-devbus Àð ¹7ÿÿÿÿÄ Ëdisabledinternal-regs !simple-bus¹ðsdramc@1400#!marvell,armada-xp-sdram-controllerÀcache-controller@8000!arm,pl310-cacheÀ€Òàì2scu@c000!arm,cortex-a9-scuÀÀXtimer@c200!arm,cortex-a9-global-timerÀ  @ Ätimer@c600!arm,cortex-a9-twd-timerÀÆ  @ Äinterrupt-controller@d000!arm,cortex-a9-gicK\ÀÐÁqi2c@11000+!marvell,mv78230-a0-i2cmarvell,mv64xxx-i2cÀ  @ÄËokayy€‰“defaulteeprom@53 !atmel,24c02ÀS¡gpio-expander@20 !nxp,pca9555ªºÀ q"pcie1_0_clkreqÆÏÕÛpcie1.0-clkreqpcie1_0_w_disableÆÏåÛpcie1.0-w-disableusb3_ilimitÆÏÕÛusb3-current-limitusb3_powerÆÏð Ûusb3-powerm2_devslpÆÏ å Ûm.2 devslppcie2_0_clkreqÆÏÕÛpcie2.0-clkreqpcie2_0_w_disableÆÏåÛpcie2.0-w-disablemcp3021@4c!microchip,mcp3021ÀLeeprom@52 !atmel,24c02ÀR¡i2c@11100+!marvell,mv78230-a0-i2cmarvell,mv64xxx-i2cÀ  @ÄËokayy† ‰“defaultq#serial@12000!!marvell,armada-38x-uartns16550aÀ ü @ ÄËokay‰“defaultserial@12100!!marvell,armada-38x-uartns16550aÀ!ü @ ÄËokay‰“defaultpinctrl@18000À€ !marvell,mv88f6828-pinctrlge-rgmii-pins-0Dmpp6mpp7mpp8mpp9mpp10mpp11mpp12mpp13mpp14mpp15mpp16mpp17 ge0q ge-rgmii-pins-1Hmpp21mpp27mpp28mpp29mpp30mpp31mpp32mpp37mpp38mpp39mpp40mpp41 ge1i2c-pins-0 mpp2mpp3 i2c0qmdio-pins mpp4mpp5 geqref-clk-pins-0mpp45 refref-clk-pins-1mpp46 refspi-pins-0mpp22mpp23mpp24mpp25 spi0spi-pins-1mpp56mpp57mpp58mpp59 spi1qnand-pinsNmpp22mpp34mpp23mpp33mpp38mpp28mpp40mpp42mpp35mpp36mpp25mpp30mpp32 devnand-rbmpp41 nanduart-pins-0 mpp0mpp1 ua0quart-pins-1 mpp19mpp20 ua1sdhci-pins<mpp48mpp49mpp50mpp52mpp53mpp54mpp55mpp57mpp58mpp59 sd0sata-pins-0mpp20 sata0sata-pins-1mpp19 sata1sata-pins-2mpp47 sata2sata-pins-3mpp44 sata3microsom-phy-clk-pinsmpp45 refqmicrosom-sdhci-pins$mpp21mpp28mpp37mpp38mpp39mpp40 sd0qi2c1-pins mpp26mpp27 i2c1qclearfog-sdhci-cd-pinsmpp20 gpioqmikro-pins mpp22mpp29 gpiomikro-spi-pinsmpp43 spi1q!mikro-uart-pins mpp24mpp25 ua1qclearfog-dsa0-clk-pinsmpp46 refqclearfog-dsa0-pins mpp23mpp41 gpioqspi1-cs-pinsmpp55 spi1q rear-button-pinsmpp34 gpioq$gpio@18100+!marvell,armada-370-gpiomarvell,orion-gpioÀ@À 1gpiopwm; ªºB\K0@5678Äqgpio@18140+!marvell,armada-370-gpiomarvell,orion-gpioÀ@@È 1gpiopwm;ªºB\K0@:;<=Äq%system-controller@18200M!marvell,armada-380-system-controllermarvell,armada-370-xp-system-controllerÀ‚clock-gating-control@18220 !marvell,armada-380-gating-clockÀ‚ ÄMq phy@18300!marvell,armada-380-comphy 1comphyconfÀƒ„`phy@0ÀZphy@1ÀZqphy@2ÀZphy@3ÀZphy@4ÀZphy@5ÀZqmvebu-sar@18600!marvell,armada-380-core-clockÀ†Mqmbus-controller@20000!marvell,mbus-controllerÀ€ Pqinterrupt-controller@20a00 !marvell,mpicÀ ÐpXK\e @qtimer@203001!marvell,armada-380-timermarvell,armada-xp-timerÀ0@0Pf    Ä  tnbclkfixedwatchdog@20300!marvell,armada-380-wdtÀ4‚` Ä  tnbclkfixed f@ cpurst@20800!marvell,armada-370-cpu-resetÀmpcore-soc-ctrl@20d20#!marvell,armada-380-mpcore-soc-ctrlÀ lcoherency-fabric@21010$!marvell,armada-380-coherency-fabricÀpmsu@22000!marvell,armada-380-pmsuÀ ethernet@70000!marvell,armada-370-netaÀ@fÄ €&HËokay‰ “defaultŽ  ’rgmii-id› ª·ethernet@30000!marvell,armada-370-netaÀ@f Ä Ëokayª·› Å’sgmiiqfixed-linkÊèÐethernet@34000!marvell,armada-370-netaÀ@@f Ä Ëokayª·› Üin-band-statusÅ’sgmiiäusb@58000!marvell,orion-ehciÀ€ @Ä Ëokayxor@60800)!marvell,armada-380-xormarvell,orion-xorÀ Ä Ëokayxor00 @èöxor01 @èöxor@60900)!marvell,armada-380-xormarvell,orion-xorÀ  Ä Ëokayxor10 @Aèöxor11 @Bèömdio@72004!marvell,orion-mdioÀ Ä ‰“defaultËokayethernet-phy@0Àq switch@4!marvell,mv88e6085À‰“defaultportsport@0À lan5port@1À lan4port@2À lan3port@3À lan2port@4À lan1port@5À cpu&fixed-linkÊèÐport@6À lan6fixed-linkÊèÐcrypto@90000!marvell,armada-38x-cryptoÀ 1regs@ Ä    tcesa0cesa1cesaz0cesaz1/Drtc@a3800!marvell,armada-380-rtcÀ 8 „   1rtcrtc-soc @Ëokaysata@a8000!marvell,armada-380-ahciÀ €  @Ä Ëokaybm@c8000!marvell,armada-380-neta-bmÀ €¬Ä ]Ëokayq sata@e0000!marvell,armada-380-ahciÀ  @Ä Ëokayclock@e4250!!marvell,armada-380-corediv-clockÀBP MÄjnandqthermal@e8078!marvell,armada380-thermalÀ@x@pËokaynand-controller@d0000"!marvell,armada370-nand-controllerÀ T @TÄ Ëdisabledsdhci@d8000!marvell,armada-380-sdhci1sdhcimbusconf-sdio3À € À„T @Ä }Ëokay“ ¦‰“default¯»usb3@f0000!marvell,armada-380-xhciÀ@@@ @Ä Ëokayusb3@f8000!marvell,armada-380-xhciÀ€@À@ @Ä Ëokaysa-sram0 !mmio-sram À Ä ¹ qsa-sram1 !mmio-sram À Ä ¹ qbm-bppi !mmio-sram À ¹ Ä ÇËokayqspi@10600)!marvell,armada-380-spimarvell,orion-spi ÀðPÔ @Ä Ëdisabledspi@10680)!marvell,armada-380-spimarvell,orion-spi Àð€PÔ @?ÄËokay ‰ !“defaultspi-flash@0!w25q32jedec,spi-norÀß-ÆÀpcie!marvell,armada-370-pcieËokayñpciýÿP¹‚ð ‚ð ‚@ð@ ‚€ð€ ‚èà‚èà‚ØЂ¸°pcie@1,0ñpci‚ ÀK@¹‚‚ÿ% 8FXÄ  Ëdisabledpcie@2,0ñpci‚ ÀK@¹‚‚ÿ% 8!FXÄ Ëokay j"pcie@3,0ñpci‚@ ÀK@¹‚‚ÿ% 8FFXÄ Ëokay j"pcie@4,0ñpci‚ € À K@¹‚‚ÿ% 8GFXÄ  Ëdisabledclocksmainpll !fixed-clockMy;šÊqoscillator !fixed-clockMy}x@q cpusvmarvell,armada-380-smpcpu@0ñcpu!arm,cortex-a9Àcpu@1ñcpu!arm,cortex-a9ÀmemoryñmemoryÀchosen„serial0:115200n8regulator-3p3v!regulator-fixed3P3VŸ2Z ·2Z Ïqsfp!sff,sfpã# ë"  ô" " "  Ðqgpio-keys !gpio-keys‰$“defaultbutton_0  Rear Button Ï%8J #address-cells#size-cellsmodelcompatiblegpio0gpio1serial0serial1ethernet1ethernet2ethernet3interrupts-extendedcontrollerinterrupt-parentpcie-mem-aperturepcie-io-aperturerangesregclocksstatuscache-unifiedcache-levelarm,double-linefill-incrarm,double-linefill-wraparm,double-linefillprefetch-datainterrupts#interrupt-cellsinterrupt-controllerphandleclock-frequencypinctrl-0pinctrl-namespagesizegpio-controller#gpio-cellsgpio-hoggpiosinputline-nameoutput-lowoutput-highreg-shiftreg-io-widthmarvell,pinsmarvell,functionreg-namesngpios#pwm-cells#clock-cells#phy-cellsmsi-controllerclock-namestx-csum-limitphyphy-modebuffer-managerbm,pool-longbm,pool-shortphysspeedfull-duplexmanagedsfpdmacap,memcpydmacap,xordmacap,memsetmarvell,reg-initlabelethernetmarvell,crypto-sramsmarvell,crypto-sram-sizeinternal-memclock-output-namesmrvl,clk-delay-cyclesbus-widthcd-gpiosno-1-8-vvmmc-supplywp-invertedno-memory-wccell-indexspi-max-frequencydevice_typemsi-parentbus-rangeassigned-addressesinterrupt-map-maskinterrupt-mapmarvell,pcie-portmarvell,pcie-lanereset-gpiosenable-methodstdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-oni2c-buslos-gpiomod-def0-gpiotx-disable-gpiotx-fault-gpiomaximum-power-milliwattlinux,can-disablelinux,code