K8E(E,Hardkernel ODROID-C1%2hardkernel,odroid-c1amlogic,meson8bsoc 2simple-bus=cbus@c1100000 2simple-busD  = system-controller@4000,2amlogic,meson-hhi-sysctrlsimple-mfdsysconD@H clock-controller2amlogic,meson8b-clkc P Wxtalddr_pllcpHpower-controller2amlogic,meson8b-pwrc}XBCKO Fdblkpic_dchdmi_apbhdmi_systemvencivencpvdacvenclviuvencrdmaPWvpu GHassist@7c002amlogic,meson-mx-assistsysconD|rng@8100&2amlogic,meson8b-rngamlogic,meson-rngDPWcoreserial@84c02amlogic,meson8b-uartD  disabledP Wxtalpclkbaudserial@84dc2amlogic,meson8b-uartD K disabledP Wxtalpclkbaudi2c@85002amlogic,meson6-i2cD   disabledPpwm@85502amlogic,meson8b-pwmDP disabledpwm@86502amlogic,meson8b-pwmDPokaydefaultPWclkin0clkin1H,adc@8680,2amlogic,meson8b-saradcamlogic,meson-saradcD4 Iokay P Wclkincore# 7 Ctemperature_calibT H*serial@87002amlogic,meson8b-uartD ] disabledP Wxtalpclkbaudi2c@87c02amlogic,meson6-i2cD   disabledPphy@880032amlogic,meson8b-usb2-phyamlogic,meson-mx-usb2-phy`D  disabledP72Wusb_generalusb"Hphy@882032amlogic,meson8b-usb2-phyamlogic,meson-mx-usb2-phy`D okayP73Wusb_generalusb"Hmmc@8c20+2amlogic,meson8b-sdioamlogic,meson-mx-sdioD  okayP  Wcoreclkin defaultslot@1 2mmc-slotDokayku}  5spi@8c802amlogic,meson6-spifcD disabledmmc@8e00*2amlogic,meson8-sdhcamlogic,meson-mx-sdhcDB Nokay$P!Wclkin0clkin1clkin2clkin3pclkdefaultk}u interrupt-controller@988022amlogic,meson-gpio-intcamlogic,meson8b-gpio-intcD  @ABCDEFGokayHwatchdog@99002amlogic,meson8b-wdtD timer@99402amlogic,meson6-timerD@0   P  Wxtalpclkreset-controller@44042amlogic,meson8b-resetDDpHanalog-top@81a8"2amlogic,meson8b-analog-topsysconDpwm@86c02amlogic,meson8b-pwmD disabledclock-measure@87582amlogic,meson8b-clk-measureDXpinctrl@98802amlogic,meson8b-cbus-pinctrlD=Hbanks@80b0 D( 086muxpullpull-enablegpio@P\ShJ2 Header Pin 35J2 Header Pin 36J2 Header Pin 32J2 Header Pin 31J2 Header Pin 29J2 Header Pin 18J2 Header Pin 22J2 Header Pin 16J2 Header Pin 23J2 Header Pin 21J2 Header Pin 19J2 Header Pin 33J2 Header Pin 8J2 Header Pin 10J2 Header Pin 15J2 Header Pin 13J2 Header Pin 24J2 Header Pin 26Revision (upper)Revision (lower)J2 Header Pin 7J2 Header Pin 12J2 Header Pin 11TFLASH_VDD_ENVCCK_PWM (PWM_C)I2CA_SDAI2CA_SCLI2CB_SDAI2CB_SCLVDDEE_PWM (PWM_D)HDMI_HPDHDMI_I2C_SDAHDMI_I2C_SCLETH_PHY_INTRETH_PHY_NRSTETH_TXD1ETH_TXD0ETH_TXD3ETH_TXD2ETH_RGMII_TX_CLKSD_DATA1 (SDB_D1)SD_DATA0 (SDB_D0)SD_CLKSD_CMDSD_DATA3 (SDB_D3)SD_DATA2 (SDB_D2)SD_CDN (SD_DET_N)SDC_D0 (EMMC)SDC_D1 (EMMC)SDC_D2 (EMMC)SDC_D3 (EMMC)SDC_D4 (EMMC)SDC_D5 (EMMC)SDC_D6 (EMMC)SDC_D7 (EMMC)SDC_CLK (EMMC)SDC_RSTn (EMMC)SDC_CMD (EMMC)BOOT_SELETH_RXD1ETH_RXD0ETH_RX_DVRGMII_RX_CLKETH_RXD3ETH_RXD2ETH_TXENETH_PHY_REF_CLK_25MOUTETH_MDCETH_MDIOH eth-rgmiiHmuxxeth_tx_clketh_tx_eneth_txd1_0eth_txd0_0eth_rx_clketh_rx_dveth_rxd1eth_rxd0eth_mdio_eneth_mdceth_ref_clketh_txd2eth_txd3eth_rxd3eth_rxd2 etherneteth-rmiimux[xeth_tx_eneth_txd1_0eth_txd0_0eth_rx_clketh_rx_dveth_rxd1eth_rxd0eth_mdio_eneth_mdc etherneti2c-amuxxi2c_sda_ai2c_sck_ai2c_asd-bH mux2xsd_d0_bsd_d1_bsd_d2_bsd_d3_bsd_clk_bsd_cmd_bsd_bsdxc-cHmux6xsdxc_d0_csdxc_d13_csdxc_d47_csdxc_clk_csdxc_cmd_csdxc_cpwm-c1Hmuxxpwm_c1pwm_cpwm-dHmuxxpwm_dpwm_duart-b0muxxuart_tx_b0uart_rx_b0uart_buart-b0-cts-rtsmuxxuart_cts_b0uart_rts_b0uart_bcache-controller@c42000002arm,pl310-cacheD    H bus@c4300000 2simple-busD0 =0interrupt-controller@10002arm,cortex-a9-gicD Hscu@02arm,cortex-a5-scuDtimer@2002arm,cortex-a5-global-timerD   P~ disabledtimer@6002arm,cortex-a5-twd-timerD   P~aobus@c8100000 2simple-busD =ir-receiver@4802amlogic,meson6-irD  okaydefaultserial@4c0+2amlogic,meson8b-uartamlogic,meson-ao-uartD ZokayP  Wxtalpclkbauddefaulti2c@5002amlogic,meson6-i2cD  \ disabledP rtc@7402amlogic,meson8b-rtcD@ H disabledP pmu@e02amlogic,meson8b-pmusysconDHpinctrl@842amlogic,meson8b-aobus-pinctrlD =Hao-bank@14D,$6muxpullgpio@P\hUART TXUART RXTF_3V3N_1V8_ENUSB_HUB_RST_NUSB_OTG_PWRENJ7 Header Pin 2IR_INJ7 Header Pin 4J7 Header Pin 6J7 Header Pin 5J7 Header Pin 7HDMI_CECSYS_LEDH)usb-hub+4@usb-hub-resetuart_ao_aHmuxxuart_tx_ao_auart_rx_ao_auart_aoremoteHmux xremote_inputremoteusb@c90400002amlogic,meson8b-usbsnps,dwc2D J Ousb2-phyYhzhost disabledPAWotgusb@c90c00002amlogic,meson8b-usbsnps,dwc2D  J Ousb2-phyhostokayP@Wotgethernet@c941000022amlogic,meson8b-dwmacsnps,dwmac-3.70asnps,dwmacDA@ macirqokay P$__*Wstmmacethclkin0clkin1timing-adjustment+ stmmacethdefault rgmii-id7 Cmac-addressmdio2snps,dwmac-mdioethernet-phy@0D'8  )Hsram@d9000000 2mmio-sramD =smp-sram@1ff802amlogic,meson8b-smp-sramDbootrom@d9040000 2amlogic,meson-mx-bootromsysconDsecbus@da000000 2simple-busD` =`nvmem@02amlogic,meson8b-efuseD P:Wcorecalib@1f4DH mac@1b4DHxtal-clk 2fixed-clock n6xtalcHcpuscpu@2000cpu2arm,cortex-a5< DMamlogic,meson8b-smp[!P o"H#cpu@2010cpu2arm,cortex-a5< DMamlogic,meson8b-smp[!P H$cpu@2020cpu2arm,cortex-a5< DMamlogic,meson8b-smp[!P H%cpu@2030cpu2arm,cortex-a5< DMamlogic,meson8b-smp[!P H&opp-table2operating-points-v2zH!opp-96000000 `opp-192000000 q `opp-312000000 `opp-408000000Q `opp-504000000 n `opp-600000000#F `opp-720000000*T `opp-8160000000, opp-1008000000<e opp-1200000000Ge opp-1320000000Ne opp-1488000000Xe opp-1536000000[e gpu-opp-table2operating-points-v2H'opp-2550000002opp-364285714opp-425000000T@opp-510000000eopp-637500000%z`pmu2arm,cortex-a5-pmu0#$%&reserved-memory=hwrom@0D bus@c8000000 2simple-busD =clock-controller@4002amlogic,meson8b-ddr-clkcD PWxtalcHbus@6000 2simple-busD` =`video-lut@48&2amlogic,meson8b-canvasamlogic,canvasDHbus@d0000000 2simple-busD  = gpu@c0000"2amlogic,meson8b-maliarm,mali-450D `&gpgpmmupppmupp0ppmmu0pp1ppmmu1NP   Wbuscore['(aliases/soc/aobus@c8100000/serial@4c0#/soc/cbus@c1100000/mmc@8c20/slot@1/soc/cbus@c1100000/mmc@8e00chosenserial0:115200n8memory0memoryD@@emmc-pwrseq2mmc-pwrseq-emmc  ?Hleds 2gpio-ledsbluec1:blue:alive )  heartbeatoffregulator-p5v02regulator-fixedP5V0"LK@:LK@H+regulator-tflash_vdd2regulator-fixed TFLASH_VDD"2Z:2ZR ] bHgpio-regulator-tf_io2regulator-gpioTF_IO"w@:2ZR )u{2Zw@Hiio-hwmon 2iio-hwmon*rtc32k-xtal-clk 2fixed-clock RTC32KcHregulator-vcc-1v82regulator-fixedVCC1V8"w@:w@R+H regulator-vcc-3v32regulator-fixedVCC3V3"2Z:2ZR+Hregulator-vcck2pwm-regulatorVCCK" `:e +,/[H"regulator-vddc-ddr2regulator-fixed DDR_VDDC"`:`R+regulator-vddee2pwm-regulatorVDDEE" `:e +,/[H(regulator-vdd-rtc2regulator-fixedVDD_RTC" : RH #address-cells#size-cellsinterrupt-parentmodelcompatiblerangesregphandleclocksclock-names#clock-cells#reset-cells#power-domain-cellsamlogic,ao-sysctrlresetsreset-namesassigned-clocksassigned-clock-ratesinterruptsstatus#pwm-cellspinctrl-0pinctrl-names#io-channel-cellsamlogic,hhi-sysctrlnvmem-cellsnvmem-cell-namesvref-supply#phy-cellsbus-widthno-sdiocap-mmc-highspeedcap-sd-highspeeddisable-wpcd-gpiosvmmc-supplyvqmmc-supplymax-frequencymmc-hs200-1_8vmmc-pwrseqinterrupt-controller#interrupt-cellsamlogic,channel-interruptsreg-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namesgroupsfunctionbias-disablebias-pull-upcache-unifiedcache-levelarm,data-latencyarm,tag-latencyarm,filter-rangesprefetch-dataprefetch-instrarm,shared-overridevdd-supplygpio-hogoutput-highline-namephysphy-namesg-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-sizedr_modeinterrupt-namesrx-fifo-depthtx-fifo-depthpower-domainsphy-handlephy-modereset-assert-usreset-deassert-usreset-gpiosclock-frequencyclock-output-namesdevice_typenext-level-cacheenable-methodoperating-points-v2cpu-supplyopp-sharedopp-hzopp-microvoltturbo-modeinterrupt-affinityno-mapmali-supplyserial0mmc0mmc1stdout-pathlabellinux,default-triggerdefault-stateregulator-nameregulator-min-microvoltregulator-max-microvoltvin-supplygpioenable-active-highgpios-statesio-channelspwm-supplypwmspwm-dutycycle-rangeregulator-boot-onregulator-always-on