&8( bHgumstix,omap3-overo-chestnut43gumstix,omap3-overoti,omap3430ti,omap3 +%7OMAP35xx Gumstix Overo on Chestnut43chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000 s/displaycpus+cpu@0arm,cortex-a8|cpucpupmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+)Gddefaultrpinmux_uart2_pins |<>@Bpinmux_i2c1_pins|pinmux_mmc1_pins0|pinmux_mmc2_pins0|(*,.02pinmux_w3cbw003c_pins|lpinmux_hsusb2_pins@|      pinmux_twl4030_pins|Apinmux_i2c3_pins|pinmux_uart3_pins|nppinmux_dss_dpi_pins| pinmux_lte430_pins|Dpinmux_backlight_pins|F!pinmux_mcspi1_pins |pinmux_ads7846_pins| scm_conf@270sysconsimple-busp0+ p0pbias_regulator@2b0ti,pbias-omap3ti,pbias-omappbias_mmc_omap2430pbias_mmc_omap2430w@-clocks+mcbsp5_mux_fck@68ti,composite-mux-clockh mcbsp5_fckti,composite-clock mcbsp1_mux_fck@4ti,composite-mux-clock mcbsp1_fckti,composite-clock mcbsp2_mux_fck@4ti,composite-mux-clock mcbsp2_fckti,composite-clock mcbsp3_mux_fck@68ti,composite-mux-clock hmcbsp3_fckti,composite-clockmcbsp4_mux_fck@68ti,composite-mux-clock hmcbsp4_fckti,composite-clockclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+)Gpinmux_twl4030_vpins |target-module@480a6000ti,sysc-omap2ti,syscH `DH `HH `Lrevsyscsyss ick+ H ` aes1@0 ti,omap3-aesP"  'txrxtarget-module@480c5000ti,sysc-omap2ti,syscH PDH PHH PLrevsyscsyss ick+ H P aes2@0 ti,omap3-aesP"AB'txrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clock1Yosc_sys_ck@d40 ti,mux-clock @sys_ck@1270ti,divider-clockApL!sys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clockcndpll3_m2x2_ckfixed-factor-clockcn dpll4_x2_ckfixed-factor-clockcncorex2_fckfixed-factor-clock cn"wkup_l4_ickfixed-factor-clock!cnQcorex2_d3_fckfixed-factor-clock"cncorex2_d5_fckfixed-factor-clock"cnclockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clock1omap_32k_fck fixed-clock1Cvirt_12m_ck fixed-clock1virt_13m_ck fixed-clock1]@virt_19200000_ck fixed-clock1$virt_26000000_ck fixed-clock1virt_38_4m_ck fixed-clock1Idpll4_ck@d00ti,omap3-dpll-per-clock!! D 0dpll4_m2_ck@d48ti,divider-clockA? HL#dpll4_m2x2_mul_ckfixed-factor-clock#cn$dpll4_m2x2_ck@d00ti,gate-clock$ x%omap_96m_alwon_fckfixed-factor-clock%cn,dpll3_ck@d00ti,omap3-dpll-core-clock!! @ 0dpll3_m3_ck@1140ti,divider-clockA@L&dpll3_m3x2_mul_ckfixed-factor-clock&cn'dpll3_m3x2_ck@d00ti,gate-clock'  x(emu_core_alwon_ckfixed-factor-clock(cnesys_altclk fixed-clock11mcbsp_clks fixed-clock1dpll3_m2_ck@d40ti,divider-clockA @Lcore_ckfixed-factor-clockcn)dpll1_fck@940ti,divider-clock)A @L*dpll1_ck@904ti,omap3-dpll-clock!*  $ @ 4dpll1_x2_ckfixed-factor-clockcn+dpll1_x2m2_ck@944ti,divider-clock+A DL?cm_96m_fckfixed-factor-clock,cn-omap_96m_fck@d40 ti,mux-clock-! @Hdpll4_m3_ck@e40ti,divider-clockA @L.dpll4_m3x2_mul_ckfixed-factor-clock.cn/dpll4_m3x2_ck@d00ti,gate-clock/ x0omap_54m_fck@d40 ti,mux-clock01 @;cm_96m_d2_fckfixed-factor-clock-cn2omap_48m_fck@d40 ti,mux-clock21 @3omap_12m_fckfixed-factor-clock3cnJdpll4_m4_ck@e40ti,divider-clockA@L4dpll4_m4x2_mul_ckti,fixed-factor-clock45dpll4_m4x2_ck@d00ti,gate-clock5 xdpll4_m5_ck@f40ti,divider-clockA?@L6dpll4_m5x2_mul_ckti,fixed-factor-clock67dpll4_m5x2_ck@d00ti,gate-clock7 xmdpll4_m6_ck@1140ti,divider-clockA?@L8dpll4_m6x2_mul_ckfixed-factor-clock8cn9dpll4_m6x2_ck@d00ti,gate-clock9 x:emu_per_alwon_ckfixed-factor-clock:cnfclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock) p<clkout2_src_mux_ck@d70ti,composite-mux-clock)!-; p=clkout2_src_ckti,composite-clock<=>sys_clkout2@d70ti,divider-clock>A@ pmpu_ckfixed-factor-clock?cn@arm_fck@924ti,divider-clock@ $Aemu_mpu_alwon_ckfixed-factor-clock@cngl3_ick@a40ti,divider-clock)A @LAl4_ick@a40ti,divider-clockAA @LBrm_ick@c40ti,divider-clockBA @Lgpt10_gate_fck@a00ti,composite-gate-clock!  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gpt2_gate_fck@1000ti,composite-gate-clock!Sgpt2_mux_fck@1040ti,composite-mux-clockC!@Tgpt2_fckti,composite-clockSTgpt3_gate_fck@1000ti,composite-gate-clock!Ugpt3_mux_fck@1040ti,composite-mux-clockC!@Vgpt3_fckti,composite-clockUVgpt4_gate_fck@1000ti,composite-gate-clock!Wgpt4_mux_fck@1040ti,composite-mux-clockC!@Xgpt4_fckti,composite-clockWXgpt5_gate_fck@1000ti,composite-gate-clock!Ygpt5_mux_fck@1040ti,composite-mux-clockC!@Zgpt5_fckti,composite-clockYZgpt6_gate_fck@1000ti,composite-gate-clock![gpt6_mux_fck@1040ti,composite-mux-clockC!@\gpt6_fckti,composite-clock[\gpt7_gate_fck@1000ti,composite-gate-clock!]gpt7_mux_fck@1040ti,composite-mux-clockC!@^gpt7_fckti,composite-clock]^gpt8_gate_fck@1000ti,composite-gate-clock! _gpt8_mux_fck@1040ti,composite-mux-clockC!@`gpt8_fckti,composite-clock_`gpt9_gate_fck@1000ti,composite-gate-clock! agpt9_mux_fck@1040ti,composite-mux-clockC!@bgpt9_fckti,composite-clockabper_32k_alwon_fckfixed-factor-clockCcncgpio6_dbck@1000ti,gate-clockcgpio5_dbck@1000ti,gate-clockcgpio4_dbck@1000ti,gate-clockcgpio3_dbck@1000ti,gate-clockcgpio2_dbck@1000ti,gate-clockc wdt3_fck@1000ti,wait-gate-clockc per_l4_ickfixed-factor-clockBcndgpio6_ick@1010ti,omap3-interface-clockdgpio5_ick@1010ti,omap3-interface-clockdgpio4_ick@1010ti,omap3-interface-clockdgpio3_ick@1010ti,omap3-interface-clockdgpio2_ick@1010ti,omap3-interface-clockd wdt3_ick@1010ti,omap3-interface-clockd uart3_ick@1010ti,omap3-interface-clockd uart4_ick@1010ti,omap3-interface-clockdgpt9_ick@1010ti,omap3-interface-clockd gpt8_ick@1010ti,omap3-interface-clockd gpt7_ick@1010ti,omap3-interface-clockdgpt6_ick@1010ti,omap3-interface-clockdgpt5_ick@1010ti,omap3-interface-clockdgpt4_ick@1010ti,omap3-interface-clockdgpt3_ick@1010ti,omap3-interface-clockdgpt2_ick@1010ti,omap3-interface-clockdmcbsp2_ick@1010ti,omap3-interface-clockdmcbsp3_ick@1010ti,omap3-interface-clockdmcbsp4_ick@1010ti,omap3-interface-clockdmcbsp2_gate_fck@1000ti,composite-gate-clock mcbsp3_gate_fck@1000ti,composite-gate-clockmcbsp4_gate_fck@1000ti,composite-gate-clockemu_src_mux_ck@1140 ti,mux-clock!efg@hemu_src_ckti,clkdm-gate-clockhipclk_fck@1140ti,divider-clockiA@Lpclkx2_fck@1140ti,divider-clockiA@Latclk_fck@1140ti,divider-clockiA@Ltraceclk_src_fck@1140 ti,mux-clock!efg@jtraceclk_fck@1140ti,divider-clockj A@Lsecure_32k_fck fixed-clock1kgpt12_fckfixed-factor-clockkcnwdt1_fckfixed-factor-clockkcnsecurity_l4_ick2fixed-factor-clockBcnlaes1_ick@a14ti,omap3-interface-clockl rng_ick@a14ti,omap3-interface-clockl sha11_ick@a14ti,omap3-interface-clockl des1_ick@a14ti,omap3-interface-clockl cam_mclk@f00ti,gate-clockmcam_ick@f10!ti,omap3-no-wait-interface-clockBcsi2_96m_fck@f00ti,gate-clocksecurity_l3_ickfixed-factor-clockAcnnpka_ick@a14ti,omap3-interface-clockn icr_ick@a10ti,omap3-interface-clockM des2_ick@a10ti,omap3-interface-clockM mspro_ick@a10ti,omap3-interface-clockM mailboxes_ick@a10ti,omap3-interface-clockM ssi_l4_ickfixed-factor-clockBcnusr1_fck@c00ti,wait-gate-clock! sr2_fck@c00ti,wait-gate-clock! sr_l4_ickfixed-factor-clockBcndpll2_fck@40ti,divider-clock)A@Lodpll2_ck@4ti,omap3-dpll-clock!o$@4pdpll2_m2_ck@44ti,divider-clockpADLqiva2_ck@0ti,wait-gate-clockqmodem_fck@a00ti,omap3-interface-clock! sad2d_ick@a10ti,omap3-interface-clockA mad2d_ick@a18ti,omap3-interface-clockA mspro_fck@a00ti,wait-gate-clock ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock" rssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock" @$sssi_ssr_fck_3430es2ti,composite-clockrstssi_sst_fck_3430es2fixed-factor-clocktcn hsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clockL ssi_ick_3430es2@a10ti,omap3-ssi-interface-clocku usim_gate_fck@c00ti,composite-gate-clockH  sys_d2_ckfixed-factor-clock!cnwomap_96m_d2_fckfixed-factor-clockHcnxomap_96m_d4_fckfixed-factor-clockHcnyomap_96m_d8_fckfixed-factor-clockHcnzomap_96m_d10_fckfixed-factor-clockHcn {dpll5_m2_d4_ckfixed-factor-clockvcn|dpll5_m2_d8_ckfixed-factor-clockvcn}dpll5_m2_d16_ckfixed-factor-clockvcn~dpll5_m2_d20_ckfixed-factor-clockvcnusim_mux_fck@c40ti,composite-mux-clock(!wxyz{|}~ @Lusim_fckti,composite-clockusim_ick@c10ti,omap3-interface-clockQ  dpll5_ck@d04ti,omap3-dpll-clock!!  $ L 4dpll5_m2_ck@d50ti,divider-clockA PLvsgx_gate_fck@b00ti,composite-gate-clock) core_d3_ckfixed-factor-clock)cncore_d4_ckfixed-factor-clock)cncore_d6_ckfixed-factor-clock)cnomap_192m_alwon_fckfixed-factor-clock%cncore_d2_ckfixed-factor-clock)cnsgx_mux_fck@b40ti,composite-mux-clock - @sgx_fckti,composite-clocksgx_ick@b10ti,wait-gate-clockA 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'lis33-3v3-regregulator-fixedlis33-3v3-reg2Z2Zlis33-1v8-regregulator-fixedlis33-1v8-regw@w@displaysamsung,lte430wq-f0cpanel-dpi lcd43ddefaultr portendpoint \  panel-timing1a     )      % 2 <ads7846-regregulator-fixed ads7846-reg2Z2Zbacklightgpio-backlightddefaultr!  Lleds gpio-ledsddefaultr"heartbeat overo:red:gpio21  ]heartbeatgpio22 overo:blue:gpio22 gpio_keys gpio-keysddefaultr#+button0 button0 W qbutton1 button1 W qregulator-vddvarioregulator-fixed vddvarioregulator-vdd33aregulator-fixedvdd33a compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-points-v2#cooling-cellsphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsstatuspagesizeVdd-supplyVdd_IO-supplyst,click-single-xst,click-single-yst,click-single-zst,click-thresh-xst,click-thresh-yst,click-thresh-zst,irq1-clickst,irq2-clickst,wakeup-x-lost,wakeup-x-hist,wakeup-y-lost,wakeup-y-hist,wakeup-z-lost,wakeup-z-hist,min-limit-xst,min-limit-yst,min-limit-zst,max-limit-xst,max-limit-yst,max-limit-z#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxwakeup-sourceti,dual-voltpbias-supplyvmmc-supplybus-widthvqmmc-supplycap-sdio-irqnon-removable#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,mux-add-datagpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-devicepwmsmax-brightnesslinux,default-triggerti,modelti,mcbspstartup-delay-usenable-active-highreset-gpiosenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activedefault-onlinux,code