\8WD(JW (,haoyu,marsboard-rk3066rockchip,rk3066a7MarsBoard RK3066aliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/mmc@1021c000f/mmc@10214000l/mmc@10218000r/serial@10124000z/serial@10126000/serial@20064000/serial@20068000/spi@20070000/spi@20074000bus ,simple-busdma-controller@20018000,arm,pl330arm,primecell @ apb_pclkdma-controller@2001c000,arm,pl330arm,primecell @ apb_pclk  disableddma-controller@20078000,arm,pl330arm,primecell @ apb_pclkoscillator ,fixed-clockn6!.xin24mgpu@10090000",rockchip,rk3066-maliarm,mali-400  buscoreAQfx  disabledx5mgpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3}cache-controller@10138000,arm,pl310-cache8scu@1013c000,arm,cortex-a9-scuglobal-timer@1013c200,arm,cortex-a9-global-timer     disabledlocal-timer@1013c600,arm,cortex-a9-twd-timer   interrupt-controller@1013d000,arm,cortex-a9-gicserial@10124000&,rockchip,rk3066-uartsnps,dw-apb-uart@ "baudclkapb_pclk@L okaytxrxdefaultserial@10126000&,rockchip,rk3066-uartsnps,dw-apb-uart` #baudclkapb_pclkAM okaytxrxdefaultqos@1012d000,syscon !qos@1012e000,syscon  qos@1012f000,syscon qos@1012f080,syscon qos@1012f100,syscon qos@1012f180,syscon qos@1012f200,syscon qos@1012f280,syscon usb@10180000,rockchip,rk3066-usbsnps,dwc2 otg otg#2@@ A Fusb2-phy okayusb@101c0000 ,snps,dwc2 otg hostA Fusb2-phy okayethernet@10204000,rockchip,rk3066-emac @< P D hclkmacref]dgrmii okayp t default  ethernet-phy@0 mmc@10214000,rockchip,rk2928-dw-mshc!@ Hbiuciurx-txfQreset okaydefaultmmc@10218000,rockchip,rk2928-dw-mshc! Ibiuciurx-txfRreset  disableddefaultmmc@1021c000,rockchip,rk2928-dw-mshc! Jbiuciurx-txfSreset  disabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd @reboot-mode,syscon-reboot-mode@RBRBRB RBpower-controller!,rockchip,rk3066-power-controllerpower-domain@7POpower-domain@6  power-domain@8!grf@20008000,syscon  i2c@2002d000,rockchip,rk3066-i2c  (P i2cP  disableddefault"i2c@2002f000,rockchip,rk3066-i2c  )P Qi2c okaydefault#tps@2d-$%% %,%8&D&P%\% ,ti,tps65910regulatorsregulator@0ivcc_rtcxvrtcregulator@1ivcc_ioxvio&regulator@2ivdd_arm '`xvdd19regulator@3ivcc_ddr '`xvdd2regulator@5 ivcc18_cifxvdig1regulator@6ivdd_11xvdig2regulator@7ivcc_25xvpllregulator@8ivcc_18xvdacregulator@9 ivcc25_hdmix vaux1regulator@10ivcca_33x vaux2regulator@11 ivcc_rmii vaux33 regulator@12 ivcc28_cifx vmmcregulator@4vdd3regulator@13 vbbpwm@20030000,rockchip,rk2928-pwm F  disableddefault'pwm@20030010,rockchip,rk2928-pwm F  disableddefault(watchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt K 3 okaypwm@20050020,rockchip,rk2928-pwm  G  disableddefault)pwm@20050030,rockchip,rk2928-pwm 0G okaydefault*Gi2c@20056000,rockchip,rk3066-i2c ` *P Ri2c  disableddefault+i2c@2005a000,rockchip,rk3066-i2c  +P Si2c  disableddefault,i2c@2005e000,rockchip,rk3066-i2c  4P Ti2c  disableddefault-serial@20064000&,rockchip,rk3066-uartsnps,dw-apb-uart @ $baudclkapb_pclkBN okaytxrxdefault.serial@20068000&,rockchip,rk3066-uartsnps,dw-apb-uart  %baudclkapb_pclkCO okay txrxdefault/saradc@2006c000,rockchip,saradc  GJsaradcapb_pclkfW saradc-apb  disabledspi@20070000,rockchip,rk3066-spiEHspiclkapb_pclk &   txrx  disableddefault0123spi@20074000,rockchip,rk3066-spiFIspiclkapb_pclk ' @  txrx  disableddefault4567cpusrockchip,rk3066-smpcpu@0cpu,arm,cortex-a988+@ Oa* s* 'g8<@J9cpu@1cpu,arm,cortex-a98J9display-subsystem,rockchip,display-subsystemU:;sram@10080000 ,mmio-sram smp-sram@0,rockchip,rk3066-smp-sramPvop@1010c000,rockchip,rk3066-vop aclk_vopdclk_vophclk_vop}fdef axiahbdclk  disabledport:endpoint@0[<@vop@1010e000,rockchip,rk3066-vop aclk_vopdclk_vophclk_vop}fghi axiahbdclk  disabledport;endpoint@0[=Ahdmi@10116000,rockchip,rk3066-hdmi`  @hclkdefault>?}P   disabledportsport@0endpoint@0[@<endpoint@1[A=port@1i2s@10118000,rockchip,rk3066-i2s  defaultBKi2s_clki2s_hclktxrxk  disabledi2s@1011a000,rockchip,rk3066-i2s  defaultCLi2s_clki2s_hclktxrxk  disabledi2s@1011c000,rockchip,rk3066-i2s  defaultDMi2s_clki2s_hclk  txrxk  disabledclock-controller@20000000,rockchip,rk3066a-cru P !@A^_ Qׄ#gрxhрxhtimer@2000e000,snps,dw-apb-timer-osc  .VD timerpclkefuse@20010000,rockchip,rk3066a-efuse @[ pclk_efusecpu_leakage@17timer@20038000,snps,dw-apb-timer-osc  ,TB timerpclktimer@2003a000,snps,dw-apb-timer-osc  -UC timerpclktsadc@20060000,rockchip,rk3066-tsadc ]]saradcapb_pclk f\ saradc-apb  disabledphy1,rockchip,rk3066a-usb-phyrockchip,rk3288-usb-phyP  okayusb-phy@17c|Qphyclk!usb-phy@188Rphyclk!pinctrl,rockchip,rk3066a-pinctrlP gpio0@20034000,rockchip,gpio-bank @ 6Ugpio1@2003c000,rockchip,gpio-bank  7Vgpio2@2003e000,rockchip,gpio-bank  8Wgpio3@20080000,rockchip,gpio-bank  9XHgpio4@20084000,rockchip,gpio-bank @ :Ygpio6@2000a000,rockchip,gpio-bank  <Z$pcfg_pull_defaultFpcfg_pull_noneEemacemac-xferEEEEEEEE emac-mdio EE emmcemmc-clkFemmc-cmd Femmc-rst Fhdmihdmi-hpdF?hdmii2c-xfer EE>i2c0i2c0-xfer EE"i2c1i2c1-xfer EE#i2c2i2c2-xfer EE+i2c3i2c3-xfer EE,i2c4i2c4-xfer EE-pwm0pwm0-outE'pwm1pwm1-outE(pwm2pwm2-outE)pwm3pwm3-outE*spi0spi0-clkF0spi0-cs0F3spi0-txF1spi0-rxF2spi0-cs1Fspi1spi1-clkF4spi1-cs0F7spi1-rxF6spi1-txF5spi1-cs1Fuart0uart0-xfer FFuart0-ctsFuart0-rtsFuart1uart1-xfer FFuart1-ctsFuart1-rtsFuart2uart2-xfer F F.uart3uart3-xfer FF/uart3-ctsFuart3-rtsFsd0sd0-clkFsd0-cmd Fsd0-cdFsd0-wpFsd0-bus-width1 Fsd0-bus-width4@ F F F Fsd1sd1-clkFsd1-cmdFsd1-cdFsd1-wpFsd1-bus-width1Fsd1-bus-width4@FFFFi2s0i2s0-busFF F F F F FFFBi2s1i2s1-bus`FFFFFFCi2s2i2s2-bus`FFFFFFDlan8720aphy-intEmemory@60000000memory`@vdd-log,pwm-regulator Givdd_logOOxB@dO* okaysdmmc-regulator,regulator-fixed isdmmc-supply-- )H.?&vsys-regulator,regulator-fixedivsysLK@LK@% #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1rangesreginterrupts#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclocksclock-namesphandlestatusclock-frequency#clock-cellsclock-output-namesassigned-clocksassigned-clock-ratesresetsinterrupt-namespower-domainscache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modephyphy-supplyfifo-depthreset-namesmax-frequencyvmmc-supplyoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qosvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu-supplyportsremote-endpointrockchip,playback-channelsrockchip,capture-channels#sound-dai-cells#reset-cells#phy-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinspwmsvoltage-tablegpiostartup-delay-usvin-supply