Ð þíYã8TÄ(TŒ!,rikomagic,mk808rockchip,rk3066a7Rikomagic MK808aliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/mmc@1021c000f/mmc@10214000l/mmc@10218000r/serial@10124000z/serial@10126000‚/serial@20064000Š/serial@20068000’/spi@20070000—/spi@20074000bus ,simple-busœdma-controller@20018000,arm,pl330arm,primecell£ €@§²½ØïÀ öapb_pclkdma-controller@2001c000,arm,pl330arm,primecell£ À@§²½ØïÀ öapb_pclk  disableddma-controller@20078000,arm,pl330arm,primecell£ €@§²½ØïÁ öapb_pclk oscillator ,fixed-clockn6!.xin24mgpu@10090000",rockchip,rk3066-maliarm,mali-400£ ïÅÅ öbuscoreAÅQõáfx  disabledx§5mgpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3}cache-controller@10138000,arm,pl310-cache£€‹™/scu@1013c000,arm,cortex-a9-scu£Àglobal-timer@1013c200,arm,cortex-a9-global-timer£  § ï  disabledlocal-timer@1013c600,arm,cortex-a9-twd-timer£Æ  § ïinterrupt-controller@1013d000,arm,cortex-a9-gic¥º£ÐÁserial@10124000&,rockchip,rk3066-uartsnps,dw-apb-uart£@ §"ËÕöbaudclkapb_pclkï@L  disabledâçtxrxñdefaultÿserial@10126000&,rockchip,rk3066-uartsnps,dw-apb-uart£` §#ËÕöbaudclkapb_pclkïAM  disabledâçtxrxñdefaultÿqos@1012d000,syscon£Ð qos@1012e000,syscon£à qos@1012f000,syscon£ð qos@1012f080,syscon£ð€ qos@1012f100,syscon£ñ qos@1012f180,syscon£ñ€ qos@1012f200,syscon£ò qos@1012f280,syscon£ò€ usb@10180000,rockchip,rk3066-usbsnps,dwc2£ §ïÃöotg otg#2€€@@ A Fusb2-phy okayusb@101c0000 ,snps,dwc2£ §ïÉöotg hostA Fusb2-phy okayethernet@10204000,rockchip,rk3066-emac£ @< §P ïÄD öhclkmacref]dgrmii  disabledmmc@10214000,rockchip,rk2928-dw-mshc£!@ §ïÀHöbiuciuâ çrx-txpfQ{reset okayúð€‡úð€ñdefaultÿ •Ÿ±Âmmc@10218000,rockchip,rk2928-dw-mshc£!€ §ïÁIöbiuciuâ çrx-txpfR{reset okayñdefault ÿ•ÎÂmmc@1021c000,rockchip,rk2928-dw-mshc£!À §ïÂJöbiuciuâ çrx-txpfS{reset  disabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd£ @reboot-mode,syscon-reboot-modeÜ@ãRBÃïRBÃýRBà  RBÃpower-controller!,rockchip,rk3066-power-controllerpower-domain@7£ˆïÃľ¿ÍÎPÇÖOÊÐÙÈÑÉÒ-power-domain@6£ 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disabledspi@20070000,rockchip,rk3066-spiïEHöspiclkapb_pclk §&£ â çtxrx  disabledñdefaultÿ'()*spi@20074000,rockchip,rk3066-spiïFIöspiclkapb_pclk §'£ @â çtxrx  disabledñdefaultÿ+,-.cpusQrockchip,rk3066-smpcpu@0_cpu,arm,cortex-a9k/£8|›@Ö O€íØa€*ˆ s€*ˆ 'ÀÈà°ÀÈàÂÀg8œ@ïcpu@1_cpu,arm,cortex-a9k/£display-subsystem,rockchip,display-subsystem›01sram@10080000 ,mmio-sram£ œsmp-sram@0,rockchip,rk3066-smp-sram£Pvop@1010c000,rockchip,rk3066-vop£Àœ § ïþÍöaclk_vopdclk_vophclk_vop}fdef {axiahbdclk okayport0endpoint@0£¡26vop@1010e000,rockchip,rk3066-vop£àœ §ïÄ¿Îöaclk_vopdclk_vophclk_vop}fghi {axiahbdclk  disabledport1endpoint@0£¡37hdmi@10116000,rockchip,rk3066-hdmi£`  §@ïÙöhclkñdefaultÿ45}P  okayportsport@0£endpoint@0£¡62endpoint@1£¡7  disabled3port@1£endpoint¡8?i2s@10118000,rockchip,rk3066-i2s£€  §ñdefaultÿ9ïKÆöi2s_clki2s_hclkâçtxrx±Ìæ  disabledi2s@1011a000,rockchip,rk3066-i2s£   § ñdefaultÿ:ïLÇöi2s_clki2s_hclkâçtxrx±Ìæ  disabledi2s@1011c000,rockchip,rk3066-i2s£À  §ñdefaultÿ;ïMÈöi2s_clki2s_hclkâ  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N<<i2c2i2c2-xfer N<<"i2c3i2c3-xfer N<<#i2c4i2c4-xfer N<<$pwm0pwm0-outN<pwm1pwm1-outN<pwm2pwm2-outN< pwm3pwm3-outN<!spi0spi0-clkN='spi0-cs0N=*spi0-txN=(spi0-rxN=)spi0-cs1N=spi1spi1-clkN=+spi1-cs0N=.spi1-rxN=-spi1-txN=,spi1-cs1N=uart0uart0-xfer N==uart0-ctsN=uart0-rtsN=uart1uart1-xfer N==uart1-ctsN=uart1-rtsN=uart2uart2-xfer N= =%uart3uart3-xfer N==&uart3-ctsN=uart3-rtsN=sd0sd0-clkN= sd0-cmdN = sd0-cdN= sd0-wpN=sd0-bus-width1N =sd0-bus-width4@N = = = =sd1sd1-clkN=sd1-cmdN=sd1-cdN=sd1-wpN=sd1-bus-width1N=sd1-bus-width4@N====i2s0i2s0-busN== = = = = ===9i2s1i2s1-bus`N======:i2s2i2s2-bus`N======;usb-hosthost-drvN=@usb-otgotg-drvN=Bsdmmcsdmmc-pwrN=Dsdiowifi-pwrN<Echosen\serial2:115200n8memory@60000000£`@_memorygpio-leds ,gpio-ledsled-0hmk808:blue:power n>toff ‚default-onhdmi_con,hdmi-connectorfcportendpoint¡?8vcc-io,regulator-fixed˜vcc_io§2Z ¿2Z Ausb-host-regulator,regulator-fixed× ê>ÿ@ñdefaultï ˜host-pwr§LK@¿LK@† Ausb-otg-regulator,regulator-fixed× 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#address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1rangesreginterrupts#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclocksclock-namesphandlestatusclock-frequency#clock-cellsclock-output-namesassigned-clocksassigned-clock-ratesresetsinterrupt-namespower-domainscache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modefifo-depthreset-namesmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeedvmmc-supplynon-removableoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qos#pwm-cells#io-channel-cellsenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencyportsremote-endpointrockchip,playback-channelsrockchip,capture-channels#sound-dai-cells#reset-cells#phy-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinsstdout-pathlabelgpiosdefault-statelinux,default-triggerregulator-nameregulator-min-microvoltregulator-max-microvoltenable-active-highgpioregulator-always-onstartup-delay-usvin-supply