s8k(kl),mundoreader,bq-edison2qcrockchip,rk31887BQ Edison2 Quad-Corealiases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/mmc@1021c000f/mmc@10214000l/mmc@10218000r/serial@10124000z/serial@10126000/serial@20064000/serial@20068000/spi@20070000/spi@20074000bus ,simple-busdma-controller@20018000,arm,pl330arm,primecell @ apb_pclkXdma-controller@2001c000,arm,pl330arm,primecell @ apb_pclk  disableddma-controller@20078000,arm,pl330arm,primecell @ apb_pclkoscillator ,fixed-clockn6!.xin24mgpu@10090000",rockchip,rk3188-maliarm,mali-400  buscoreAQfx okayx 5mgpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3}cache-controller@10138000,arm,pl310-cacheLscu@1013c000,arm,cortex-a9-scuglobal-timer@1013c200,arm,cortex-a9-global-timer     disabledlocal-timer@1013c600,arm,cortex-a9-twd-timer   interrupt-controller@1013d000,arm,cortex-a9-gicserial@10124000&,rockchip,rk3188-uartsnps,dw-apb-uart@ "baudclkapb_pclk@L okaydefault bluetooth,brcm,bcm43438-bt   *default serial@10126000&,rockchip,rk3188-uartsnps,dw-apb-uart` #baudclkapb_pclkAM okaydefault qos@1012d000,syscon 'qos@1012e000,syscon &qos@1012f000,syscon !qos@1012f080,syscon #qos@1012f100,syscon $qos@1012f180,syscon "qos@1012f200,syscon qos@1012f280,syscon %usb@10180000,rockchip,rk3066-usbsnps,dwc2 otg9otgASb@@ q vusb2-phy okayusb@101c0000 ,snps,dwc2 otg9hostq vusb2-phy okayethernet@10204000,rockchip,rk3188-emac @< D hclkmacrefdrmii  disabledmmc@10214000,rockchip,rk2928-dw-mshc!@ Hbiuciurx-txfQreset okaydefaultmmc@10218000,rockchip,rk2928-dw-mshc! Ibiuciurx-txfRreset okay!default /wifi@1,brcm,bcm4329-fmac mhost-wake<defaultmmc@1021c000,rockchip,rk2928-dw-mshc! Jbiuciurx-txfSreset okay!default/ pmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd @Zreboot-mode,syscon-reboot-modeP@WRBcRBqRB RBpower-controller!,rockchip,rk3188-power-controllerpower-domain@7hO!"#$%power-domain@6 &power-domain@8'grf@20008000,syscon i2c@2002d000,rockchip,rk3188-i2c  (i2cP okaydefault(accelerometer@29 ,st,lis3de)default)1000-10001i2c@2002f000,rockchip,rk3188-i2c  )Qi2c okaydefault*tmp108@48 ,ti,tmp108H+default,rtc@51,haoyu,hym8563Q default-!.xin32kibattery@55 ,ti,bq27541U.5pmic@5a,active-semi,act8846Zdefault/0111 1 1,1regulatorsREG18VCC_DDRGO_OwREG28VDD_LOGGB@_OwREG38VDD_ARMG Y_pwNREG48VCC_IOG-_-wREG58VDD_10GB@_B@wREG68VDD_12GO_OwREG7 8VCC18_CIFGw@_w@wREG88VCCA_33G2Z_2ZwREG98VCC_TPG2Z_2ZwREG10 8VCCIO_WLG*_*wREG118VCC_18Gw@_w@wCREG12 8VCC28_CIFG*_*wlcharger@6b ,ti,bq24196kdefault 23405.usb-otg-vbuspwm@20030000,rockchip,rk2928-pwm F  disableddefault6pwm@20030010,rockchip,rk2928-pwm F okaydefault7_watchdog@2004c000 ,rockchip,rk3188-wdtsnps,dw-wdt K 3 okaypwm@20050020,rockchip,rk2928-pwm  G  disableddefault8pwm@20050030,rockchip,rk2928-pwm 0G  disableddefault9i2c@20056000,rockchip,rk3188-i2c ` *Ri2c okaydefault:touchscreen@3e,edt,edt-ft5506>+default;<   i2c@2005a000,rockchip,rk3188-i2c  +Si2c okaydefault=i2c@2005e000,rockchip,rk3188-i2c  4Ti2c okaydefault>codec@1b,realtek,rt5616Kmclk8serial@20064000&,rockchip,rk3188-uartsnps,dw-apb-uart @ $baudclkapb_pclkBN okaydefault?serial@20068000&,rockchip,rk3188-uartsnps,dw-apb-uart  %baudclkapb_pclkCO okaydefault @ABsaradc@2006c000,rockchip,saradc  IGJsaradcapb_pclkfW saradc-apb okay[Cspi@20070000(,rockchip,rk3188-spirockchip,rk3066-spiEHspiclkapb_pclk &   txrx  disableddefaultDEFGspi@20074000(,rockchip,rk3188-spirockchip,rk3066-spiFIspiclkapb_pclk ' @  txrx  disableddefaultHIJKcpusgrockchip,rk3066-smpcpu@0ucpu,arm,cortex-a9L@MfNcpu@1ucpu,arm,cortex-a9LMfNcpu@2ucpu,arm,cortex-a9LMfNcpu@3ucpu,arm,cortex-a9LMfNopp_table0,operating-points-v2Mopp-312000000 Y@opp-504000000 nHopp-600000000#F~opp-8160000000,opp-1008000000<g8opp-1200000000G0opp-1416000000Tfropp-1608000000_"pdisplay-subsystem,rockchip,display-subsystemOPsram@10080000 ,mmio-sram smp-sram@0,rockchip,rk3066-smp-sramPvop@1010c000,rockchip,rk3188-vop aclk_vopdclk_vophclk_vop}fdef axiahbdclk okayportOendpointQcvop@1010e000,rockchip,rk3188-vop aclk_vopdclk_vophclk_vop}fghi axiahbdclk okaydefaultRSTUVportPtimer@2000e000,,rockchip,rk3188-timerrockchip,rk3288-timer  .EW pclktimertimer@200380a0,,rockchip,rk3188-timerrockchip,rk3288-timer   @BZ pclktimeri2s@1011a000(,rockchip,rk3188-i2srockchip,rk3066-i2s  defaultWKi2s_clki2s_hclkXXtxrx-8 okaysound@1011e000,,rockchip,rk3188-spdifrockchip,rk3066-spdif 8N mclkhclkXtx defaultY okayclock-controller@20000000,rockchip,rk3188-cru !G@A^_ Q#g nрxhрxhefuse@20010000,rockchip,rk3188-efuse @[ pclk_efusecpu_leakage@17phy0,rockchip,rk3188-usb-phyrockchip,rk3288-usb-phy okayusb-phy@10cT Qphyclk!usb-phy@11cTRphyclk!pinctrl,rockchip,rk3188-pinctrl_Zgpio0@2000a000,rockchip,rk3188-gpio-bank0  6Ul|gpio1@2003c000,rockchip,gpio-bank  7Vl|+gpio2@2003e000,rockchip,gpio-bank  8Wl|gpio3@20080000,rockchip,gpio-bank  9Xl|pcfg_pull_up\pcfg_pull_downpcfg_pull_none[emmcemmc-clk[emmc-cmd\emmc-rst[emacemac-xfer[[[[[[[[emac-mdio [[i2c0i2c0-xfer [[(i2c1i2c1-xfer [[*i2c2i2c2-xfer [[:i2c3i2c3-xfer [[=i2c4i2c4-xfer [[>lcdc1lcdc1-dclk[Rlcdc1-den[Slcdc1-hsync[Tlcdc1-vsync[Ulcdc1-rgb24[[[[[[[[[ [ [ [ [ [[[[[[[[[[[Vpwm0pwm0-out[6pwm1pwm1-out[7pwm2pwm2-out[8pwm3pwm3-out[9spi0spi0-clk\Dspi0-cs0\Gspi0-tx\Espi0-rx\Fspi0-cs1\spi1spi1-clk\Hspi1-cs0\Kspi1-rx\Jspi1-tx\Ispi1-cs1\uart0uart0-xfer \[uart0-cts[uart0-rts[uart1uart1-xfer \[ uart1-cts[uart1-rts[uart2uart2-xfer \ [?uart3uart3-xfer  \ [@uart3-cts [Auart3-rts [Bsd0sd0-clk[sd0-cmd[sd0-cd[sd0-wp [sd0-pwr[sd0-bus-width1[sd0-bus-width4@[[[[sd1sd1-clk[sd1-cmd[sd1-cd[sd1-wp[sd1-bus-width1[sd1-bus-width4@[[[[i2s0i2s0-bus`[[[[[[Wspdifspdif-tx[Ypcfg-output-high^pcfg-output-low]act8846dvs0-ctl]/pmic-int \0bq24196charger-int\2chg-ctl^3chg-det[chg-en]dc-det [otg-en ^4cameracif0-pdn [cif1-pdn [cif-avdd-en[kdisplaylcd-cs[flcd-en[nft5606tp-int\;tp-rst[<hdmihdmi-int\hdmi-rst [hym8563rtc-int \-keyspwr-hold\bpwr-key\`lis3degsensor-int[)mmcsdmmc-pwr[qtmp108tmp-alrt[,usbv5-drv[motg-drv [ousb-int\ark903bt-host-wake\ bt-reg-on[ bt-rst^ bt-wake[ wifi-host-wake\wifi-reg-on[jmemory@60000000umemory`backlight,pwm-backlight1 _aegpio-keys ,gpio-keysdefault`apower tGPIO Key Powerd'wake-on-usb Wake-on-USB 'gpio-poweroff,gpio-poweroff defaultb5 lvds-encoder,ti,sn75lvds83lvds-encoderportsport@0endpointcQport@1endpointdhpanel,innolux,ee101ia-01dpanel-lvdsEe Odefaultfg\vesa-24ispanel-timingJ|   portendpointhdsdio-pwrseq,mmc-pwrseq-simplei ext_clockdefaultj cif-avdd-regulator,regulator-fixed 8avdd-cifG*_* +defaultklvcc-5v-regulator,regulator-fixed8vcc-5vGLK@_LK@ defaultm1plcd-regulator,regulator-fixed8vcc-lcd defaultnPgusb-otg-regulator,regulator-fixed8vcc-otgGLK@_LK@  defaultopsdmmc-regulator,regulator-fixed8vcc-sdG2Z_2Z defaultqemmc-vccq-regulator,regulator-fixed 8vccq-emmcG*_* vsys-regulator,regulator-fixed8vsysGLK@_LK@1 #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1rangesreginterrupts#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclocksclock-namesphandlestatusclock-frequency#clock-cellsclock-output-namesassigned-clocksassigned-clock-ratesresetsinterrupt-namespower-domainscache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthpinctrl-namespinctrl-0max-speeddevice-wakeup-gpioshost-wakeup-gpiosshutdown-gpiosdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfphy-modedmasdma-namesfifo-depthreset-namesbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplykeep-power-in-suspendmmc-pwrseqnon-removablevqmmc-supplybrcm,drive-strengthoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qosrotation-matrixvdd-supply#thermal-sensor-cellspower-suppliesvp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onti,system-minimum-microvoltmonitored-batteryomit-battery-class#pwm-cellsreset-gpiostouchscreen-inverted-ytouchscreen-size-ytouchscreen-size-xtouchscreen-swapped-x-y#sound-dai-cells#io-channel-cellsvref-supplyenable-methoddevice_typenext-level-cacheclock-latencyoperating-points-v2cpu-supplyopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsremote-endpointrockchip,playback-channelsrockchip,capture-channels#reset-cells#phy-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disablerockchip,pinsoutput-highoutput-lowpower-supplypwmsautorepeatlinux,codelabellinux,input-typedebounce-intervalwakeup-sourceactive-delay-msbacklightenable-gpiosdata-mappingheight-mmwidth-mmhactivevactivehback-porchhfront-porchhsync-lenvback-porchvfront-porchvsync-lengpiostartup-delay-usvin-supplyenable-active-highregulator-boot-on