TR8N(jN!,Rockchip RK3228 Evaluation board$2rockchip,rk3228-evbrockchip,rk3228aliases=/serial@11010000E/serial@11020000M/serial@11030000U/spi@11090000cpuscpu@f00Zcpu2arm,cortex-a7fjq@pscicpu@f01Zcpu2arm,cortex-a7fjqpscicpu@f02Zcpu2arm,cortex-a7fjqpscicpu@f03Zcpu2arm,cortex-a7fjqpsciopp_table02operating-points-v2opp-408000000Q~@opp-600000000#Fopp-8160000000,B@opp-1008000000<opp-1200000000Gtxbus 2simple-buspdma@110f00002arm,pl330arm,primecellf@ 0apb_pclk arm-pmu2arm,cortex-a7-pmu0LMNO<psci2arm,psci-1.0arm,psci-0.2smctimer2arm,armv7-timerO0   sn6oscillator 2fixed-clocksn6xin24mdisplay-subsystem2rockchip,display-subsystemi2s1@100b0000(2rockchip,rk3228-i2srockchip,rk3066-i2sf @ 0i2s_clki2s_hclkQ  txrxdefault  disabledi2s0@100c0000(2rockchip,rk3228-i2srockchip,rk3066-i2sf @ 0i2s_clki2s_hclkP txrx disabledspdif@100d00002rockchip,rk3228-spdiff  S 0mclkhclk txdefault  disabledi2s2@100e0000(2rockchip,rk3228-i2srockchip,rk3066-i2sf@ 0i2s_clki2s_hclkR txrx disabledsyscon@11000000&2rockchip,rk3228-grfsysconsimple-mfdfio-domains"2rockchip,rk3228-io-voltage-domain disabledusb2-phy@7602rockchip,rk3228-usb2phyf` 0phyclk usb480m_phy0 disabled6otg-port$;<=otg-bvalidotg-idlinestate disabled5host-port > linestate disabled7usb2-phy@8002rockchip,rk3228-usb2phyf 0phyclk usb480m_phy1 disabled8otg-port D linestate disabled9host-port E linestate disabled:serial@110100002snps,dw-apb-uartf 7sn6MU0baudclkapb_pclkdefault   disabledserial@110200002snps,dw-apb-uartf 8sn6NV0baudclkapb_pclkdefault disabledserial@110300002snps,dw-apb-uartf 9sn6OW0baudclkapb_pclkdefaultokayefuse@110400002rockchip,rk3228-efusef G 0pclk_efuseid@7fcpu_leakage@17fi2c@110500002rockchip,rk3228-i2cf $0i2cLdefault disabledi2c@110600002rockchip,rk3228-i2cf %0i2cMdefault disabledi2c@110700002rockchip,rk3228-i2cf &0i2cNdefault disabledi2c@110800002rockchip,rk3228-i2cf '0i2cOdefault disabledspi@110900002rockchip,rk3228-spif  1AR0spiclkapb_pclkdefault disabledwatchdog@110a0000 2snps,dw-wdtf  (b disabledpwm@110b00002rockchip,rk3288-pwmf  ^0pwmdefault disabledpwm@110b00102rockchip,rk3288-pwmf  ^0pwmdefault disabledpwm@110b00202rockchip,rk3288-pwmf  ^0pwmdefault disabledpwm@110b00302rockchip,rk3288-pwmf 0 ^0pwmdefault disabledtimer@110c0000,2rockchip,rk3228-timerrockchip,rk3288-timerf  + a 0timerpclkclock-controller@110e00002rockchip,rk3228-cruf!H.kb$>#g0,eррxhррxhthermal-zonescpu-thermalSdiw tripscpu_alert0papassive!cpu_alert1$apassive"cpu_crit_ acriticalcooling-mapsmap0!0map1"0tsadc@111500002rockchip,rk3228-tsadcf :HX0tsadcapb_pclk.H>jW tsadc-apbinitdefaultsleep#$#sokay hdmi-phy@120300002rockchip,rk3228-hdmi-phyfm0sysclkrefoclkrefpclk hdmiphy_phy disabled'gpu@20000000"2rockchip,rk3228-maliarm,mali-400f Hgpgpmmupp0ppmmu0pp1ppmmu1 0buscorej~ disablediommu@200208002rockchip,iommuf    0aclkiface1 disablediommu@200304802rockchip,iommuf @ @  0aclkiface1 disabledvop@200500002rockchip,rk3228-vopf   0aclk_vopdclk_vophclk_vopjdef axiahbdclk>% disabledportendpoint@0fE&+iommu@20053f002rockchip,iommuf ?   0aclkiface1 disabled%rga@20060000(2rockchip,rk3228-rgarockchip,rk3288-rgaf  !0aclkhclksclkjkmn coreaxiahbiommu@200708002rockchip,iommuf   0aclkiface1 disabledhdmi@200a00002rockchip,rk3228-dw-hdmif  #.U'l{0iahbisfrcecdefault ()*j`hdmil'qhdmi disabledportsportendpoint@0fE+&mmc@3000000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@   Drv0biuciuciu-driveciu-sample{default ,-. disabledmmc@3001000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@   Esw0biuciuciu-driveciu-sample{default /01 disabledmmc@3002000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@ s<4`<4` Guy0biuciuciu-driveciu-sample{default 234jSresetokayusb@3004000022rockchip,rk3228-usbrockchip,rk3066-usbsnps,dwc2f0 0otgotg@ l5 qusb2-phy disabledusb@30080000 2generic-ehcif0  6l7qusb disabledusb@300a0000 2generic-ohcif0   6l7qusb disabledusb@300c0000 2generic-ehcif0   8l9qusb disabledusb@300e0000 2generic-ohcif0  8l9qusb disabledusb@30100000 2generic-ehcif0 B 8l:qusb disabledusb@30120000 2generic-ohcif0 C 8l:qusb disabledethernet@302000002rockchip,rk3228-gmacf0  macirq8~oM0stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macj8 stmmacethokay.|>,output9;DrmiiM<mdio2snps,dwmac-mdioethernet-phy@042ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22fj?X<interrupt-controller@32010000 2arm,gic-400j f22 2@ 2`   pinctrl2rockchip,rk3228-pinctrlgpio0@111100002rockchip,gpio-bankf 3@jgpio1@111200002rockchip,gpio-bankf 4Ajgpio2@111300002rockchip,gpio-bankf 5Bjgpio3@111400002rockchip,gpio-bankf 6Cjpcfg-pull-up@pcfg-pull-down?pcfg-pull-none>pcfg-pull-none-drv-12ma =sdmmcsdmmc-clk=,sdmmc-cmd=-sdmmc-bus4@====.sdiosdio-clk=/sdio-cmd=0sdio-bus4@====1emmcemmc-clk>2emmc-cmd>3emmc-bus8>>>>>>>>4gmacrgmii-pins> >>==== = =>>>> >>rmii-pins> >>== =>>>>phy-pins >>hdmihdmi-hpd?)hdmii2c-xfer >>(hdmi-cec>*i2c0i2c0-xfer >>i2c1i2c1-xfer >>i2c2i2c2-xfer >>i2c3i2c3-xfer >>spi0spi0-clk @spi0-cs0@spi0-tx @spi0-rx @spi0-cs1 @spi1spi1-clk@spi1-cs0@spi1-rx@spi1-tx@spi1-cs1@i2s1i2s1-bus> > > > >>>>> pwm0pwm0-pin>pwm1pwm1-pin>pwm2pwm2-pin >pwm3pwm3-pin >spdifspdif-tx> tsadcotp-pin>#otp-out>$uart0uart0-xfer >> uart0-cts> uart0-rts>uart1uart1-xfer  > >uart1-cts>uart1-rts >uart2uart2-xfer @>uart21-xfer  @ >uart2-cts>uart2-rts>memory@60000000Zmemoryf`@vcc-phy-regulator2regulator-fixedvcc_phyw@,w@DX; #address-cells#size-cellsinterrupt-parentmodelcompatibleserial0serial1serial2spi0device_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksenable-methodphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterrupts#dma-cellsarm,pl330-periph-burstclock-namesinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsportsdmasdma-namespinctrl-namespinctrl-0statusinterrupt-names#phy-cellsreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarity#iommu-cellsiommusremote-endpointassigned-clock-parentsphysphy-namesfifo-depthmax-frequencybus-widthrockchip,default-sample-phasecap-mmc-highspeedmmc-ddr-1_8vdisable-wpnon-removabledr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeclock_in_outphy-supplyphy-modephy-handlephy-is-integratedinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsenable-active-highregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-on