8( Xgoogle,veyron-mighty-rev5google,veyron-mighty-rev4google,veyron-mighty-rev3google,veyron-mighty-rev2google,veyron-mighty-rev1google,veyron-mightygoogle,veyronrockchip,rk3288&7Google Mightyaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/spi@ff110000/ec@0/i2c-tunnelarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12 -@;Br\ hcpu@501cpuarm,cortex-a12 -@;Brhcpu@502cpuarm,cortex-a12 -@;Brhcpu@503cpuarm,cortex-a12 -@;Brhcpu-opp-tableoperating-points-v2phopp-126000000{ opp-216000000{  opp-408000000{Q opp-600000000{#F opp-696000000{)|~opp-816000000{0,B@opp-1008000000{<opp-1200000000{Gopp-1416000000{TfrOopp-1512000000{ZJopp-1608000000{_" opp-1704000000{epopp-1800000000{kI\bus simple-busdma-controller@ff250000arm,pl330arm,primecell%@; apb_pclkh"dma-controller@ff600000arm,pl330arm,primecell`@; apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@; apb_pclkhfreserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24m h timerarm,armv7-timer0   n6;timer@ff810000rockchip,rk3288-timer  H ;a  pclktimerdisplay-subsystemrockchip,display-subsystemR mmc@ff0c0000rockchip,rk3288-dw-mshcXр ;Drvbiuciuciu-driveciu-samplef  @qresetokay}  Z $1default? I mmc@ff0d0000rockchip,rk3288-dw-mshcXр ;Eswbiuciuciu-driveciu-samplef ! @qresetokay}R_u1default ? $btmrvl@2marvell,sd8897-bt& 1default?mmc@ff0e0000rockchip,rk3288-dw-mshcXр ;Ftxbiuciuciu-driveciu-samplef "@qreset disabledmmc@ff0f0000rockchip,rk3288-dw-mshcXр ;Guybiuciuciu-driveciu-samplef #@qresetokay}u1default ? !saradc@ff100000rockchip,saradc $;I[saradcapb_pclkW qsaradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi;ARspiclkapb_pclk" " txrx ,1default?#$%&okayec@0google,cros-ec-spi& 1default?'-i2c-tunnelgoogle,cros-ec-i2c-tunnel sbs-battery@bsbs,sbs-battery 1keyboard-controllergoogle,cros-ec-keybFV iD};0DY1 d>"A#( C  \=@V B |})<?   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ispi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi;BSspiclkapb_pclk" "txrx -1default?()*+ disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi;CTspiclkapb_pclk""txrx .1default?,-./okay flash@0jedec,spi-nori2c@ff140000rockchip,rk3288-i2c >i2c;M1default?0okay2dtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c ?i2c;O1default?1 disabledi2c@ff160000rockchip,rk3288-i2c @i2c;P1default?2okay2,ts3a227e@3b ti,ts3a227e;&31default?4htrackpad@15elan,ekth3000& 1default?56i2c@ff170000rockchip,rk3288-i2c Ai2c;Q1default?7 disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7;MUbaudclkapb_pclk""txrx1default ?89:okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8;NVbaudclkapb_pclk""txrx1default?;okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9;OWbaudclkapb_pclk1default?<okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :;PXbaudclkapb_pclk""txrx1default?= disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;;QYbaudclkapb_pclk" " txrx1default?> disabledthermal-zonesreserve_thermal%;I?cpu_thermal%d;I?tripscpu_alert0Ypepassiveh@cpu_alert1Y$epassivehAcpu_critYe criticalcooling-mapsmap0p@0umap1pA0ugpu_thermal%d;I?tripsgpu_alert0Y4epassivehBgpu_critYe criticalcooling-mapsmap0pB uCtsadc@ff280000rockchip,rk3288-tsadc( %;HZtsadcapb_pclk qtsadc-apb1initdefaultsleep?DEDFHokayh?ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irqF8;fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB qstmmaceth disabledusb@ff500000 generic-ehciP ;Gusbokay#usb@ff520000 generic-ohciR );Gusb disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T ;otg9hostH usb2-phyAokayXusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X ;otg9hosto@@ I usb2-phyokayzIXusb@ff5c0000 generic-ehci\ ; disabledi2c@ff650000rockchip,rk3288-i2ce <i2c;L1default?Jokay2dpmic@1brockchip,rk808xin32kwifibt_32kin&31default ?KLM  N#/;H6UbNnN{ hregulatorsDCDC_REG1vdd_arm q qh regulator-state-memDCDC_REG2vdd_gpu 5qhregulator-state-memDCDC_REG3 vcc135_ddrregulator-state-memDCDC_REG4vcc_18w@w@hregulator-state-mem0w@LDO_REG1 vcc33_io2Z2Zh6regulator-state-mem02ZLDO_REG3vdd_10B@B@regulator-state-mem0B@LDO_REG7vdd10_lcd_pwren_h&%&%regulator-state-memSWITCH_REG1 vcc33_lcdhdregulator-state-memLDO_REG6 vcc18_codecw@w@heregulator-state-memLDO_REG4 vccio_sdw@2Zhregulator-state-memLDO_REG5 vcc33_sd2Z2Zhregulator-state-memLDO_REG8 vcc33_ccd2Z2Zregulator-state-memLDO_REG2mic_vccw@w@regulator-state-memi2c@ff660000rockchip,rk3288-i2cf =i2c;N1default?Ookay2 max98090@10maxim,max98090&Pmclk;q1default?Qhpwm@ff680000rockchip,rk3288-pwmhL1default?R;_pwmokayhpwm@ff680010rockchip,rk3288-pwmhL1default?S;_pwmokayhpwm@ff680020rockchip,rk3288-pwmh L1default?T;_pwm disabledpwm@ff680030rockchip,rk3288-pwmh0L1default?U;_pwm disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdshpower-controller!rockchip,rk3288-power-controllerWh hipower-domain@9 ;chgfdehilkj$kVWXYZ[\]^power-domain@11 ;opk_`power-domain@12 ;kapower-domain@13 ;kbcreboot-modesyscon-reboot-moderyRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruvF Hjk$#gׄeрxhрxhhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwhFedp-phyrockchip,rk3288-dp-phy;h24mokayhyio-domains"rockchip,rk3288-io-voltage-domainokay66 6 d ) 5e Busbphyrockchip,rk3288-usb-phyokayusb-phy@320 ;]phyclk  qphy-resethIusb-phy@3344;^phyclk  qphy-resethGusb-phy@348H;_phyclk  qphy-resethHwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt;p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif P;T mclkhclkftx 61default?gF disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s P 5;Ri2s_clki2s_hclkfftxrx1default?h a |okayhcrypto@ff8a0000rockchip,rk3288-crypto@ 0 ;}aclkhclksclkapb_pclk qcrypto-rstokayiommu@ff900800rockchip,iommu@ iep_mmu; aclkiface  disablediommu@ff914000rockchip,iommu @P isp_mmu; aclkiface   disabledrga@ff920000rockchip,rk3288-rga ;jaclkhclksclk i ilm qcoreaxiahbvop@ff930000rockchip,rk3288-vop  ;aclk_vopdclk_vophclk_vop i def qaxiahbdclk jokayporth endpoint@0 khendpoint@1 lh{endpoint@2 mhtendpoint@3 nhwiommu@ff930300rockchip,iommu  vopb_mmu; aclkiface i  okayhjvop@ff940000rockchip,rk3288-vop  ;aclk_vopdclk_vophclk_vop i  qaxiahbdclk ookayporth endpoint@0 phendpoint@1 qh|endpoint@2 rhuendpoint@3 shxiommu@ff940300rockchip,iommu  vopl_mmu; aclkiface i  okayhomipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ ;~d refpclk i F disabledportsportendpoint@0 thmendpoint@1 uhrlvds@ff96c000rockchip,rk3288-lvds@;g pclk_lvds1lcdc?v i F disabledportsport@0endpoint@0 whnendpoint@1 xhsdp@ff970000rockchip,rk3288-dp@ b;icdppclkydp i oqdpFokay1default?zportsport@0endpoint@0 {hlendpoint@1 |hqport@1endpoint@0 }hhdmi@ff980000rockchip,rk3288-dw-hdmi PF g;hmniahbisfrcec i okay1defaultunwedge?~hportsportendpoint@0 hkendpoint@1 hpvideo-codec@ff9a0000rockchip,rk3288-vpu   vepuvdpu; aclkhclk  i iommu@ff9a0800rockchip,iommu vpu_mmu; aclkiface  i hiommu@ff9c0440rockchip,iommu @@@ o hevc_mmu; aclkiface  disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ jobmmugpu;  i okay hCgpu-opp-tableoperating-points-v2hopp-100000000{~opp-200000000{ ~opp-300000000{B@opp-400000000{ׄopp-600000000{#Fqos@ffaa0000syscon hbqos@ffaa0080syscon hcqos@ffad0000syscon hWqos@ffad0100syscon hXqos@ffad0180syscon hYqos@ffad0400syscon hZqos@ffad0480syscon h[qos@ffad0500syscon hVqos@ffad0800syscon h\qos@ffad0880syscon h]qos@ffad0900syscon h^qos@ffae0000syscon haqos@ffaf0000syscon h_qos@ffaf0080syscon h`efuse@ffb40000rockchip,rk3288-efuse ;q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400  @ @ `   hpinctrlrockchip,rk3288-pinctrlF1defaultsleep?gpio0@ff750000rockchip,gpio-banku Q;@  %   1PMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LAP_LID_INT_LEC_IN_RWAC_PRESENT_APRECOVERY_SW_LOTP_OUTHOST1_PWR_ENUSBOTG_PWREN_HAP_WARM_RESET_HnFALUT2I2C0_SDA_PMICI2C0_SCL_PMICSUSPEND_LUSB_INTh3gpio1@ff780000rockchip,gpio-bankx R;A  %  gpio2@ff790000rockchip,gpio-banky S;B  %  M 1CONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_LBL_PWR_ENAVDD_1V8_DISP_ENhgpio3@ff7a0000rockchip,gpio-bankz T;C  %   1FLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio4@ff7b0000rockchip,gpio-bank{ U;D  %   1UART0_RXDUART0_TXDUART0_CTSUART0_RTSSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEhgpio5@ff7c0000rockchip,gpio-bank| V;E  %  A 1SPI0_CLKSPI0_CS0SPI0_TXDSPI0_RXDVCC50_HDMI_ENhgpio6@ff7d0000rockchip,gpio-bank} W;F  %   1I2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HALS_INTINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETSDMMC_D0SDMMC_D1SDMMC_D2SDMMC_D3SDMMC_CLKSDMMC_CMDhPgpio7@ff7e0000rockchip,gpio-bank~ X;G  %   1LCDC_BLPWM_LOGBL_ENTRACKPAD_INTTPM_INT_HSDMMC_DET_LAP_FLASH_WP_LEC_INTCPU_NMIDVSOKSDMMC_WPEDP_HPDDVS1nFALUT1LCD_ENDVS2VCC5V_GOOD_HI2C4_SDA_TPI2C4_SCL_TPI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXDh gpio8@ff7f0000rockchip,gpio-bank Y;H  %  ^ 1RAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 Ahdmi-cec-c7 Ahdmi-ddc Ah~hdmi-ddc-unwedge Ahvcc50-hdmi-en Ahpcfg-output-low Ohpcfg-pull-up Zhpcfg-pull-down ghpcfg-pull-none vhpcfg-pull-none-12ma v hsuspendglobal-pwroff Ahddrio-pwroff Ahddr0-retention Ahddr1-retention Asuspend-l-wake Ahsuspend-l-sleep Ahedpedp-hpd A hzi2c0i2c0-xfer AhJi2c1i2c1-xfer Ah0i2c2i2c2-xfer A  hOi2c3i2c3-xfer Ah1i2c4i2c4-xfer Ah2i2c5i2c5-xfer Ah7i2s0i2s0-bus` Ahhlcdclcdc-ctl@ Ahvsdmmcsdmmc-clk Ahsdmmc-cmd Ahsdmmc-cd Asdmmc-bus1 Asdmmc-bus4@ Ahsdmmc-cd-disabled Ahsdmmc-cd-pin Ahsdmmc-wp-pin A hsdio0sdio0-bus1 Asdio0-bus4@ Ahsdio0-cmd Ahsdio0-clk Ahsdio0-cd Asdio0-wp Asdio0-pwr Asdio0-bkpwr Asdio0-int Awifienable-h Ahbt-enable-l Abt-host-wake Abt-host-wake-l Ahbt-dev-wake-sleep Ahbt-dev-wake-awake Ahbt-dev-wake Asdio1sdio1-bus1 Asdio1-bus4@ Asdio1-cd Asdio1-wp Asdio1-bkpwr Asdio1-int Asdio1-cmd Asdio1-clk Asdio1-pwr A emmcemmc-clk Ahemmc-cmd Ah emmc-pwr A emmc-bus1 Aemmc-bus4@ Aemmc-bus8 Ah!emmc-reset A hspi0spi0-clk A h#spi0-cs0 A h&spi0-tx Ah$spi0-rx Ah%spi0-cs1 Aspi1spi1-clk A h(spi1-cs0 A h+spi1-rx Ah*spi1-tx Ah)spi2spi2-cs1 Aspi2-clk Ah,spi2-cs0 Ah/spi2-rx Ah.spi2-tx A h-uart0uart0-xfer Ah8uart0-cts Ah9uart0-rts Ah:uart1uart1-xfer A h;uart1-cts A uart1-rts A uart2uart2-xfer Ah<uart3uart3-xfer Ah=uart3-cts A uart3-rts A uart4uart4-xfer Ah>uart4-cts A uart4-rts A tsadcotp-pin A hDotp-out A hEpwm0pwm0-pin AhRpwm1pwm1-pin AhSpwm2pwm2-pin AhTpwm3pwm3-pin AhUgmacrgmii-pins A rmii-pins Aspdifspdif-tx A hgpcfg-pull-none-drv-8ma v hpcfg-pull-up-drv-8ma Z pcfg-output-high hbuttonspwr-key-l Ahap-lid-int-l Ahpmicpmic-int-l AhKdvs-1 A hLdvs-2 AhMrebootap-warm-reset-h A hrecovery-switchrec-mode-l A tpmtpm-int-h Awrite-protectfw-wp-ap Acodechp-det Ahint-codec AhQmic-det A hheadsetts3a227e-int-l Ah4backlightbl_pwr_en A hbl-en Ahlcdlcd-en Ahavdd-1v8-disp-en A hchargerac-present-ap Ahcros-ecec-int Ah'trackpadtrackpad-int Ah5usb-hosthost1-pwr-en A husbotg-pwren-h A hbuck-5vdrv-5v Ahchosen serial2:115200n8memorymemorypower-button gpio-keys1default?power Power 3 t dgpio-restart gpio-restart 3 1default? emmc-pwrseqmmc-pwrseq-emmc?1default hsdio-pwrseqmmc-pwrseq-simple; ext_clock1default? hvcc-5vregulator-fixedvcc_5vLK@LK@   1default?hNvcc33-sysregulator-fixed vcc33_sys2Z2Z hvcc50-hdmiregulator-fixed vcc50_hdmi N  1default?vdd-logicpwm-regulator vdd_logic   { )~psound!rockchip,rockchip-audio-max980901default?