@8(t wm,wm8750 &VIA APC8750cpuscpu,cpuarm,arm1176jzfmemory,memory8aliases?pinctrl@d8110000wm,wm8750-pinctrl8defaulti2cpmc@d8130000via,vt8500-pmc8clocksref24M fixed-clock$n6ref25M fixed-clock$}x@pllawm,wm8750-pll-clock48pllbwm,wm8750-pll-clock48pllcwm,wm8750-pll-clock48plldwm,wm8750-pll-clock48 pllewm,wm8750-pll-clock48armvia,vt8500-device-clock4;ahbvia,vt8500-device-clock4;apbvia,vt8500-device-clock4; ddrvia,vt8500-device-clock4;uart0via,vt8500-device-clock4GTR uart1via,vt8500-device-clock4GTR uart2via,vt8500-device-clock4GTR uart3via,vt8500-device-clock4GTR uart4via,vt8500-device-clock4GTR uart5via,vt8500-device-clock4GTRpwmvia,vt8500-device-clock4;PGPRsdhcvia,vt8500-device-clock4;0]?GPRi2c0clkvia,vt8500-device-clock4;GPRi2c1clkvia,vt8500-device-clock4;GPR pwm@d8220000jvia,vt8500-pwm8"4timer@d8130100via,vt8500-timer8($ehci@d8007900via,vt8500-ehci8yuhci@d8007b00platform-uhci8{uhci@d8008d00platform-uhci8serial@d8200000via,vt8500-uart8 @ 4 uokayserial@d82b0000via,vt8500-uart8+@!4  udisabledserial@d8210000via,vt8500-uart8!@/4  udisabledserial@d82c0000via,vt8500-uart8,@24  udisabledserial@d8370000via,vt8500-uart87@4  udisabledserial@d8380000via,vt8500-uart88@+4 udisabledrtc@d8100000via,vt8500-rtc80sdhc@d800a000wm,wm8505-sdhc84|i2c@d8280000wm,wm8505-i2c8(4$i2c@d8320000wm,wm8505-i2c824$ #address-cells#size-cellscompatiblemodeldevice_typeregserial0serial1serial2serial3serial4serial5i2c0i2c1rangesinterrupt-parentinterrupt-controller#interrupt-cellsphandleinterruptsgpio-controller#gpio-cellspinctrl-namespinctrl-0wm,pinswm,functionwm,pull#clock-cellsclock-frequencyclocksdivisor-regenable-regenable-bitdivisor-mask#pwm-cellsstatusbus-widthsdon-inverted